# US 12,119,065 B2 · Non-volatile memory with zoned control for limiting programming for different groups of non-volatile memory cells

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- Number: US 12,119,065 B2
- Document ID: US12119065B2
- Status: Granted
- Kind: B2
- Application number: 17/709,762
- Filed: 2022-03-31
- Published: 2023-10-05
- Granted: 2024-10-15
- Earliest claimed: 2022-03-31
- Assignees: SanDisk Technoloiges LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Xiaochen Zhu; Lito De La Rama; Yi Song; Jiacen Guo; Jiahui Yuan
- Web page: https://patentgrep.com/patent/US12119065B2

## CPC

- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/10: Programming or data input circuits
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- H10W 80/00: Direct bonding of chips, wafers or substrates
- G11C 11/5671: {using charge trapping in an insulator}
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10W 90/00: Package configurations
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A non-volatile memory system limits the amount of programming for a first type of group of non-volatile memory cells based on a first parameter such that a maximum number of programming pulses applied to the first type of group of non-volatile memory cells to program to the last data state after the first type of group of non-volatile memory cells completed programming to the other data states is X programming pulses. The non-volatile memory system limits the amount of programming for a second type of group of the non-volatile memory cells based on a second parameter such that a maximum number of programming pulses applied to the second type of group of non-volatile memory cells to program to the last data state after the second type of group of non-volatile memory cells completed programming to the other data states is Y programming pulses.

## Claims

### Claim 1

A non-volatile storage apparatus, comprising:
a non-volatile memory structure comprising multiple word lines and multiple groups of non-volatile memory cells configured to store data in a set of data states comprising an erased data state and middle data states and a last data state, the multiple groups of non-volatile memory cells comprise a first group of the non-volatile memory cells and a second group of the non-volatile memory cells in a same block of non-volatile memory cells, the block of non-volatile memory cells is divided into a first outer sub-block and a second outer sub-block and a first inner sub-block between the first outer sub-block and the second outer sub-block, all of the non-volatile memory cells of the first group of non-volatile memory cells are in the first inner sub-block, all of the non-volatile memory cells of the second group of non-volatile memory cells are in the first outer sub-block, each of the multiple word lines is connected to the first outer sub-block and the second outer sub-block and the first inner sub-block; and
one or more control circuits connected to the non-volatile memory structure, the one or more control circuits are configured to:
store a value for X, X is a first parameter;
store a value for Y, Y is a second parameter, X is different than Y; and
program the first group of non-volatile memory cells separately from programming the second group of non-volatile memory cells using programming pulses such that a maximum number of programming pulses applied to the first group of non-volatile memory cells to program to the last data state after the first group of non-volatile memory cells completed programming to the middle data states is X programming pulses and a maximum number of programming pulses applied to the second group of non-volatile memory cells to program to the last data state after the second group of non-volatile memory cells completed programming to the middle data states is Y programming pulses.

### Claim 2 (depends on 1)

The non-volatile storage apparatus of claim 1, wherein the one or more control circuits are configured to program the first group of non-volatile memory cells separately from programming the second group of non-volatile memory cells by:
programming a first subset of the first group of non-volatile memory cells to the middle data states by applying programming pulses of a program signal to the first group of non-volatile memory cells until the first subset of the first group of non-volatile memory cells successfully reach the middle data states;
after programming the first subset of the first group of non-volatile memory cells to the middle data states, programming a second subset of the first group of non-volatile memory cells to the last data state by applying no more than the X number of programming pulses of the program signal to the first group of non-volatile memory cells;
programming a first subset of the second group of non-volatile memory cells to the middle data states by applying programming pulses of the program signal to the second group of non-volatile memory cells until the first subset of the second group of non-volatile memory cells successfully reach the middle data states; and
after programming the first subset of the second group of non-volatile memory cells to the middle data states, programming a second subset of the second group of non-volatile memory cells to the last data state by applying no more than the Y number of programming pulses of the program signal to the second group of non-volatile memory cells.

### Claim 3 (depends on 2)

The non-volatile storage apparatus of claim 2, wherein:
the programming pulses of the program signal are voltage pulses that increase in magnitude from pulse to pulse.

### Claim 4 (depends on 1)

The non-volatile storage apparatus of claim 1, wherein:
the set of data states correspond to a plurality of threshold voltage distributions; and
the set of data states includes the last data state that corresponds to a threshold voltage distribution having highest threshold voltages of the plurality of threshold voltage distributions.

### Claim 5 (depends on 1)

The non-volatile storage apparatus of claim 1, wherein:
all of the non-volatile memory cells of the first group of non-volatile memory cells are part of vertical NAND strings and are connected to a first word line;
all of the non-volatile memory cells of the second group of non-volatile memory cells are part of vertical NAND strings and are connected to a second word line;
the non-volatile memory structure is positioned on a memory die; and
the one or more control circuits are positioned on a control die that is directly bonded to the memory die.

### Claim 6

A non-volatile storage apparatus, comprising:
a non-volatile memory structure comprising multiple groups of non-volatile memory cells, the non-volatile memory structure is configured to store a first parameter and a second parameter; and
one or more control circuits connected to the non-volatile memory structure, the one or more control circuits are configured to program the multiple groups of non-volatile memory cells including limiting the amount of programming for a first group of the non-volatile memory cells based on the first parameter and limiting the amount of programming for a second group of the non-volatile memory cells based on the second parameter, the first parameter is capable of storing multiple values including a value indicating to disable the limiting of the amount of programming for the first group of the non-volatile memory cells and the second parameter is capable of storing multiple values including a value indicating to disable the limiting of the amount of programming for the second group of the non-volatile memory cells.

### Claim 7

A method of operating non-volatile storage, comprising:
programming a first subset of a first group of non-volatile memory cells to a first set of data states by applying doses of a program signal to the first group of non-volatile memory cells until the first subset of the first group of non-volatile memory cells successfully reach the first set of data states;
after programming the first subset of the first group of non-volatile memory cells to the first set of data states, programming a second subset of the first group of non-volatile memory cells to an additional data state by applying no more than a first number of doses of the program signal to the first group of non-volatile memory cells;
programming a first subset of a second group of non-volatile memory cells to the first set of data states by applying doses of the program signal to the second group of non-volatile memory cells until the first subset of the second group of non-volatile memory cells successfully reach the first set of data states; and
after programming the first subset of the second group of non-volatile memory cells to the first set of data states, programming a second subset of the second group of non-volatile memory cells to the additional data state by applying no more than a second number of doses of the program signal to the second group of non-volatile memory cells, the first number of doses is different than the second number of doses;
wherein the first group of non-volatile memory cells and the second group of non-volatile memory cells are part of a block of non-volatile memory cells that comprises sub-blocks including a first outer sub-block, a second outer sub-block and inner sub-blocks between the first outer sub-block and the second outer sub-block, all of the sub-blocks comprise tiers including an upper tier and a lower tier, all of the non-volatile memory cells of the first group of non-volatile memory cells are in one or more tiers of the sub-blocks other than the upper tier of the first outer sub-block and the upper tier of the second outer sub-block, all of the non-volatile memory cells of the second group of non-volatile memory cells are in the upper tier of the first outer sub-block and the first number of doses is less than the second number of doses.

### Claim 8 (depends on 7)

The method of claim 7, further comprising;
storing a first parameter that indicates the first number of doses, the programming the second subset of the second group of non-volatile memory cells to the additional data state is limited to no more than the first number of doses of the program signal based on the first parameter; and
storing a second parameter that indicates the second number of doses, the programming the second subset of the second group of non-volatile memory cells to the additional data state is limited to no more than the second number of doses of the program signal based on the second parameter.

### Claim 9 (depends on 7)

The method of claim 7, wherein:
all of the non-volatile memory cells of the first group of non-volatile memory cells are connected to a first word line; and
all of the non-volatile memory cells of the second group of non-volatile memory cells are connected to a second word line.