# US 12,119,064 B2 · Binary to ternary convertor for multilevel memory

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- Number: US 12,119,064 B2
- Document ID: US12119064B2
- Status: Granted
- Kind: B2
- Application number: 17/114,475
- Filed: 2020-12-07
- Published: 2022-06-09
- Granted: 2024-10-15
- Earliest claimed: 2020-12-07
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Pawel Tomkiewicz; Jacek Jaworski
- Web page: https://patentgrep.com/patent/US12119064B2

## CPC

- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 16/10: Programming or data input circuits
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/30: Power supply circuits
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 2029/0411: {Online error correction}
- G11C 2213/73: Array where access device function, e.g. diode function, being merged with memorizing function of memory element
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device including a memory array comprising a plurality of memory cells, respective memory cells each comprising a storage element comprising phase change memory programmable to three unique states; and a controller comprising circuitry, the controller to convert binary data into ternary data at a ratio of three bits of binary data to two trits of ternary data and provide the ternary data to the memory array for storage.

## Claims

### Claim 1

A memory device including:
a memory array comprising a plurality of memory cells, respective memory cells each coupled between a respective wordline and a respective bitline and each comprising a storage element comprising phase change memory programmable to three unique states; and
a controller comprising circuitry, the controller to convert binary data into ternary data at a ratio of three bits of binary data to two trits of ternary data and provide the ternary data to the memory array for storage.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein a memory cell of the plurality of memory cells is to store a single trit of the ternary data.

### Claim 3 (depends on 1)

The memory device of claim 1, the controller comprising circuitry to map respective values of three bits of binary data to respective values of two trits of ternary data.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the controller is programmable to change the mapping between at least one value of three bits of binary data to at least one value of two trits of ternary data.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein the controller leaves one value of two trits unmapped to any of the values of three bits.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein the value of two trits that is unmapped corresponds to a reset state for each of two memory cells to store the trits.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the reset state corresponds to an amorphous phase in which a memory cell has a higher threshold voltage than when the memory cell is in one of the other two states.

### Claim 8 (depends on 3)

The memory device of claim 3, wherein one value of a trit value is reserved to store at least a portion of an error-correction code.

### Claim 9 (depends on 1)

The memory device of claim 1, further comprising a plurality of memory chips, wherein a first memory chip of the plurality of memory chips comprises the controller and memory array.

### Claim 10 (depends on 9)

The memory device of claim 9, further comprising a memory controller to communicate with the plurality of memory chips.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein the memory device comprises a solid state drive.

### Claim 12 (depends on 1)

The memory device of claim 1, wherein the memory device comprises a dual in-line memory module.

### Claim 13

A method comprising:
receiving binary data from a host computing device;
converting the binary data into ternary data at a ratio of three bits of binary data to two trits of ternary data; and
writing the ternary data to a memory array a plurality of memory cells, respective memory cells each coupled between a respective wordline and a respective bitline and each comprising a storage element comprising phase change memory programmable to three unique states.

### Claim 14 (depends on 13)

The method of claim 13, further comprising mapping respective values of three bits of binary data to respective values of two trits of ternary data.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
determining a value of two trits that is most susceptible to read errors; and
leaving the determined value unassigned to any of the values of three bits.

### Claim 16 (depends on 14)

The method of claim 14, further comprising leaving a value of two trits unmapped to any value of three bits, wherein the unmapped value of two trits corresponds to a reset state for each of two memory cells to store the trits.

### Claim 17 (depends on 13)

The method of claim 13, further comprising using a value of two trits to store at least a portion of an error-correction code.

### Claim 18

A system comprising:
a memory device comprising:
a device controller; and
at least one memory chip coupled to the device controller, wherein a memory chip comprises:
a memory array comprising a plurality of memory cells, respective memory cells each coupled between a respective wordline and a respective bitline and each comprising a storage element comprising phase change memory programmable to three unique states; and
a controller comprising circuitry, the controller to convert binary data into ternary data at a ratio of three bits of binary data to two trits of ternary data and provide the ternary data to the memory array for storage.

### Claim 19 (depends on 18)

The system of claim 18, further comprising a processor to generate the binary data and to communicate the binary data to the storage device.

### Claim 20 (depends on 19)

The system of claim 19, further comprising one or more of: a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.