# US 12,119,060 B2 · Content-addressable memory and electronic device including the same

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- Number: US 12,119,060 B2
- Document ID: US12119060B2
- Status: Granted
- Kind: B2
- Application number: 17/953,491
- Filed: 2022-09-27
- Published: 2023-03-30
- Granted: 2024-10-15
- Earliest claimed: 2021-09-27
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jinseong Heo; Hagyoul Bae; Seunggeol Nam; Hyunjae Lee; Dukhyun Choe
- Web page: https://patentgrep.com/patent/US12119060B2

## CPC

- G11C 15/04: using semiconductor elements
- G11C 15/046: {using non-volatile storage elements}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Provided is a content-addressable memory. The content-addressable memory may include a memory cell connected to a match line, a word line, and a search line, and the memory cell includes a first channel layer and a second channel layer doped with different dopants.

## Claims

### Claim 1

A content-addressable memory comprising:
a match line extending in a first direction;
a word line spaced apart from the match line, the word line extending parallel to the first direction;
a search line spaced apart from the match line and the word line; and
a plurality of memory cells respectively connected to the match line, the word line, and the search line,
wherein at least one of the plurality of memory cells includes
a source electrode and a drain electrode spaced apart from each other,
a first channel layer and a second channel layer doped with different dopants, the first channel layer and the second channel layer between the source electrode and the drain electrode such that a first end of the first channel layer and a first end of the second channel layer contact the source electrode and a second end of the first channel layer and a second end of the second channel layer contact the drain electrode, and
a gate electrode spaced apart from all of the first channel layer, the second channel layer, the source electrode, and the drain electrode.

### Claim 2 (depends on 1)

The content-addressable memory of claim 1, further comprising:
a substrate,
wherein the source electrode and the drain electrode are located on the substrate and are spaced apart from each other in a direction parallel to a surface of the substrate, and
the first channel layer and the second channel layer are located on the substrate and are spaced apart from each other in a thickness direction of the substrate.

### Claim 3 (depends on 1)

The content-addressable memory of claim 1, wherein a ratio of a charge mobility of the second channel layer to a charge mobility of the first channel layer is equal to or greater than 0.9 and equal to or less than 1.1.

### Claim 4 (depends on 1)

The content-addressable memory of claim 1, wherein
one of the first channel layer and the second channel layer is doped with an n-type dopant, and
an other of the first channel layer and the second channel layer is doped with a p-type dopant.

### Claim 5 (depends on 4)

The content-addressable memory of claim 4, wherein a doping concentration of the p-type dopant in the other of the first channel layer and the second channel layer is equal to or greater than a doping concentration of the n-type dopant in the one of the first channel layer and the second channel layer.

### Claim 6 (depends on 1)

The content-addressable memory of claim 1, wherein the first channel layer, the second channel layer, or both the first channel layer and the second channel layer comprise at least one of silicon (Si), germanium (Ge), an oxide semiconductor, a group III-V material, a two-dimensional (2D) material, a transition metal dichalcogenide, quantum dots (QDs), and an organic material.

### Claim 7 (depends on 1)

The content-addressable memory of claim 1, wherein a base material of the first channel layer and a base material of the second channel layer are a same material.

### Claim 8 (depends on 1)

The content-addressable memory of claim 1, wherein the at least one of the plurality of memory cells further comprises:
a first gate insulating layer surrounding the first channel layer; and
a second gate insulating layer surrounding the second channel layer,
wherein the first gate insulating layer and the second gate insulating layer are spaced apart from each other with a portion of the gate electrode therebetween.

### Claim 9 (depends on 8)

The content-addressable memory of claim 8, wherein at least one of the first gate insulating layer and the second gate insulating layer comprises a ferroelectric material.

### Claim 10 (depends on 9)

The content-addressable memory of claim 9, wherein
the ferroelectric material comprises a material represented as MO2, and
in MO2, where M is Hf, Zr, or a combination thereof, and M is a base material.

### Claim 11 (depends on 8)

The content-addressable memory of claim 8, wherein at least one of the first gate insulating layer and the second gate insulating layer further comprises at least one dopant material selected from C, Si, Ge, Sn, Pb, Al, Y, La, Gd, Mg, Ca, Sr Ba, Ti, Zr, Hf, and a combination thereof.

### Claim 12 (depends on 8)

The content-addressable memory of claim 8, wherein at least one of the first gate insulating layer and the second gate insulating layer comprises:
a first layer including a paraelectric material; and
a second layer including a ferroelectric material.

### Claim 13 (depends on 12)

The content-addressable memory of claim 12, wherein the paraelectric material comprises an oxide of a material included in at least one of the first channel layer and the second channel layer.

### Claim 14 (depends on 12)

The content-addressable memory of claim 12, wherein the paraelectric material comprises at least one of SiO, AlO, SiON, and SiN.

### Claim 15 (depends on 8)

The content-addressable memory of claim 8, wherein the gate electrode comprises:
a first gate electrode surrounding the first gate insulating layer; and
a second gate electrode surrounding the second gate insulating layer.

### Claim 16 (depends on 15)

The content-addressable memory of claim 15, wherein the first gate electrode and the second gate electrode contact each other.

### Claim 17 (depends on 15)

The content-addressable memory of claim 15, wherein the first gate electrode and the second gate electrode are spaced apart from each other by an insulating layer.

### Claim 18 (depends on 17)

The content-addressable memory of claim 17, wherein the insulating layer comprises a paraelectric material.

### Claim 19 (depends on 1)

The content-addressable memory of claim 1, wherein
the word line is connected to the source electrode,
the match line is connected to the drain electrode, and
the search line is connected to the gate electrode.

### Claim 20 (depends on 1)

An electronic device comprising:
the content-addressable memory of claim 1.