# US 12,119,058 B2 · Error correction for identifier data generated from unclonable characteristics of resistive memory

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- Number: US 12,119,058 B2
- Document ID: US12119058B2
- Status: Granted
- Kind: B2
- Application number: 17/708,541
- Filed: 2022-03-30
- Published: 2023-10-05
- Granted: 2024-10-15
- Earliest claimed: 2022-03-30
- Assignees: Crossbar, Inc.
- Applicants: Crossbar, Inc.
- Inventors: Mehdi Asnaashari
- Web page: https://patentgrep.com/patent/US12119058B2

## CPC

- G11C 13/003: {Cell access}
- G11C 13/0069: {Writing or programming circuits or methods}
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0059: {Security or protection circuits or methods}
- H03M 13/1105: {Decoding}
- H04L 9/0866: {involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics}
- G11C 2029/0411: {Online error correction}
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C 2029/5002: {Characteristic}
- G11C 2213/79: Array wherein the access device being a transistor
- H03M 13/03: Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M 13/05: using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)}
- H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes}
- H03M 13/13: Linear codes
- H03M 13/1505: {Golay Codes}
- H03M 13/1515: {Reed-Solomon codes}
- H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes}
- H03M 13/19: Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
- H03M 13/23: using convolutional codes, e.g. unit memory codes
- H03M 13/2957: {Turbo codes and decoding}
- H03M 13/3905: {Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding}
- H03M 13/41: using the Viterbi algorithm or Viterbi processors
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

## Claims

### Claim 1

A method, comprising:
initiate a physical unclonable feature (PUF) write process for generating identifier data at a resistive switching memory array;
determine a number, X, of bits for the PUF write and first addresses within the resistive switching memory array corresponding to a plurality of resistive switching memory cells targeted for the PUF write;
identify a number, P, of correction bits required for the X bits of identifier data;
allocate X+P bits of resistive memory for the X bits of identifier data plus the correction bits;
allocate X differential bits at second addresses in the resistive memory for differential cell generation of the identifier data;
electrically couple bitlines of respective pairs of bits from the first addresses and the second addresses, wherein each pair of bits comprises one resistive memory cell from the first addresses and one resistive memory cell from the second addresses;
initiate a forming pulse for the PUF write at each pair of bits at the first addresses and the second addresses;
complete the forming pulse in response to a termination condition;
read a data pattern generated in the X bits of identifier data at the first addresses in response to the forming pulse;
generate correction data for the data pattern; and
save the correction data to the P bits of the resistive memory allocated for the correction bits.

### Claim 2 (depends on 1)

The method of claim 1, further comprising receiving a command from a host device specifying the PUF write process and the first addresses within the resistive switching memory array for writing the identifier data to the resistive switching memory array, wherein initiating the PUF write process is in response to the command from the host device.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second addresses are displaced within the resistive switching memory array from the first addresses a multiple of the X bits of identifier data.

### Claim 4 (depends on 3)

The method of claim 3, wherein the second addresses are displaced 8 multiples of the X bits from the first addresses.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second addresses are displaced within the resistive switching memory array from the first addresses a multiple of the X+P bits of identifier data plus the correction bits.

### Claim 6 (depends on 5)

The method of claim 5, wherein the second addresses are displaced 8 multiples of the X+P bits of identifier data plus the correction bits.

### Claim 7 (depends on 1)

The method of claim 1, wherein the termination condition for a pair of bits comprises identifying a first program condition for the one resistive memory cell from the first addresses or for the one resistive memory cell from the second addresses.

### Claim 8 (depends on 7)

The method of claim 7, wherein completing the forming pulse further comprises identifying a first program condition for one resistive memory cell of each pair of bits from the first addresses and the second addresses.