# US 12,119,057 B2 · Read algorithms for three-dimensional crosspoint memory architectures

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- Number: US 12,119,057 B2
- Document ID: US12119057B2
- Status: Granted
- Kind: B2
- Application number: 17/540,884
- Filed: 2021-12-02
- Published: 2023-06-08
- Granted: 2024-10-15
- Earliest claimed: 2021-12-02
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Rouhollah Mousavi Iraei; Mini Goel; Raymond Zeng; Hemant P. Rao
- Web page: https://patentgrep.com/patent/US12119057B2

## CPC

- G11C 13/004: {Reading or sensing circuits or methods}
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0023: {Address circuits or decoders}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 2013/0052: {Read process characterized by the shape, e.g. form, length, amplitude of the read pulse}
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In one embodiment, a state is reach from a memory cell comprising a phase change material (PM) region and a select device (SD) region by: ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage, ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell, detecting a snap in the memory cell while ramping the voltage applied to the second address line, and determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.

## Claims

### Claim 1

A non-volatile memory device comprising:
a memory array comprising:
a plurality of non-volatile memory cells, each memory cell comprising a phase change material (PM) region and a select device (SD) region in series with the PM region; and
address lines to apply voltages across the memory cells, wherein each memory cell has a corresponding address line pair to apply voltages thereto; and
memory controller circuitry to interface with the address lines of the memory cells, the memory controller circuitry to read a state in a memory cell by:
ramping a voltage applied to a first address line of the address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage;
ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell;
detecting a snap in the memory cell while ramping the voltage applied to the second address line; and
determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the wordline and the second address line is the bitline.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the predetermined voltage is between −2.8V and −3.4 V.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the bitline and the second address line is the wordline.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the predetermined voltage is between 3.2V and 3.7V.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the memory controller circuitry is to:
determine that the memory cell has a crystalline PM region and a crystalline SD region based on the differential voltage between the first and second address lines being between 5.7V and 6.2V; and
determine that the memory cell has a crystalline PM region and an amorphous SD region based on the differential voltage between the first and second address lines being between 6.3V and 6.8V.

### Claim 7

A memory module comprising:
input/output (I/O) circuitry to couple the memory module with an external controller; and
a plurality of non-volatile memory devices, each memory device comprising:
a plurality of non-volatile memory cells, each memory cell comprising a phase change material (PM) region and a select device (SD) region in series with the PM region;
address lines to apply voltages across the memory cells, wherein each memory cell has a corresponding address line pair to apply voltages thereto; and
memory controller circuitry to interface with the address lines of the memory cells, the memory controller circuitry to read a state in a memory cell by:
ramping a voltage applied to a first address line of the address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage;
ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell;
detecting a snap in the memory cell while ramping the voltage applied to the second address line; and
determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.

### Claim 8 (depends on 7)

The memory module of claim 7, wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the wordline and the second address line is the bitline.

### Claim 9 (depends on 8)

The memory module of claim 8, wherein the predetermined voltage is between −2.8V and −3.4 V.

### Claim 10 (depends on 7)

The memory module of claim 7, wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the bitline and the second address line is the wordline.

### Claim 11 (depends on 10)

The memory module of claim 10, wherein the predetermined voltage is between 3.2V and 3.7V.

### Claim 12 (depends on 7)

The memory module of claim 7, wherein the memory controller circuitry is to:
determine that the memory cell has a crystalline PM region and a crystalline SD region based on the differential voltage between the first and second address lines being between 5.7V and 6.2V; and
determine that the memory cell has a crystalline PM region and an amorphous SD region based on the differential voltage between the first and second address lines being between 6.3V and 6.8V.

### Claim 13

A memory controller comprising:
circuitry interface with address lines of a memory cell comprising a phase change material (PM) region and a select device (SD) region in series, the circuitry to read a state in a memory cell by:
ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage;
ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell;
detecting a snap in the memory cell while ramping the voltage applied to the second address line; and
determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.

### Claim 14 (depends on 13)

The memory controller of claim 13, wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the wordline and the second address line is the bitline.

### Claim 15 (depends on 14)

The memory controller of claim 14, wherein the predetermined voltage is between −2.8V and −3.4 V.

### Claim 16 (depends on 13)

The memory controller of claim 13, wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the bitline and the second address line is the wordline.

### Claim 17 (depends on 16)

The memory controller of claim 16, wherein the predetermined voltage is between 3.2V and 3.7V.

### Claim 18 (depends on 13)

The memory controller of claim 13, wherein the circuitry is to:
determine that the memory cell has a crystalline PM region and a crystalline SD region based on the differential voltage between the first and second address lines being between 5.7V and 6.2V; and
determine that the memory cell has a crystalline PM region and an amorphous SD region based on the differential voltage between the first and second address lines being between 6.3V and 6.8V.

### Claim 19

A method of reading a state in a memory cell comprising a phase change material (PM) region and a select device (SD) region in series, the method comprising:
ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage;
ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell;
detecting a snap in the memory cell while ramping the voltage applied to the second address line; and
determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.

### Claim 20 (depends on 19)

The method of claim 19, wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the wordline and the second address line is the bitline.

### Claim 21 (depends on 20)

The method of claim 20, wherein the predetermined voltage is between −2.8V and −3.4 V.

### Claim 22 (depends on 19)

The method of claim 19, wherein each address line pair corresponding to a memory cell comprises a wordline and a bitline, the first address line is the bitline and the second address line is the wordline.

### Claim 23 (depends on 22)

The method of claim 22, wherein the predetermined voltage is between 3.2V and 3.7V.

### Claim 24 (depends on 19)

The method of claim 19, wherein the differential voltage between the first and second address lines is between 5.7V and 6.2V and the determined memory state is a state having a crystalline PM region and a crystalline SD region.

### Claim 25 (depends on 19)

The method of claim 19, wherein the differential voltage between the first and second address lines is between 6.3V and 6.8V and the determined memory state is a state having a crystalline PM region and an amorphous SD region.