# US 12,119,055 B2 · Memory device architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,055 B2 - Document ID: US12119055B2 - Status: Granted - Kind: B2 - Application number: 17/329,028 - Filed: 2021-05-24 - Published: 2021-09-09 - Granted: 2024-10-15 - Earliest claimed: 2012-10-12 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Hernan A. Castro; Everardo Torres Flores; Jeremy M. Hirst - Web page: https://patentgrep.com/patent/US12119055B2 ## CPC - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 13/0023: {Address circuits or decoders} - H10B 63/24: {of the Ovonic threshold switching type} - H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors} - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 2213/71: Three dimensional array - G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/8828: {Tellurides, e.g. GeSbTe} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array. ## Claims ### Claim 1 A method, comprising: forming a memory array comprising a plurality of sub array regions across a footprint of the memory array; forming a plurality of first electrode drivers distributed across the footprint of the memory array in a plurality of disjointed first electrode driver regions; and forming a plurality of second electrode drivers of a same type as the plurality of first electrode drivers and distributed across the footprint in a plurality of disjointed second electrode driver regions such that the plurality of first electrode drivers are oriented in a first direction and the plurality of second electrode drivers are oriented in a second direction perpendicular to the first direction, such that at least a portion of one of the plurality of disjointed first electrode driver regions and at least a portion of one of the plurality of disjointed second electrode driver regions are within each sub array region of the plurality of sub array regions, wherein each disjointed first electrode driver region of the plurality of disjointed first electrode driver regions within each sub array region spans less than a length of each corresponding sub array region. ### Claim 2 (depends on 1) The method of claim 1, wherein forming the plurality of first electrode drivers in the plurality of disjointed first electrode driver regions includes arranging first electrode driver regions of the plurality of disjointed first electrode driver regions in a repeating pattern of sub array regions across the footprint. ### Claim 3 (depends on 2) The method of claim 2, wherein forming the plurality of second electrode drivers further comprises: arranging the plurality of disjointed second electrode driver regions in the repeating pattern of sub array regions. ### Claim 4 (depends on 3) The method of claim 3, wherein arranging the plurality of disjointed first electrode driver regions and the plurality of disjointed second electrode driver regions in the repeating pattern includes alternating the plurality of disjointed first electrode driver regions with the plurality of disjointed second electrode driver regions in at least one of a first electrode lengthwise direction and a second electrode lengthwise direction. ### Claim 5 (depends on 3) The method of claim 3, wherein forming the memory array comprises forming staggered first electrodes connecting the plurality of first electrode drivers to memory cells of the memory array, and forming staggered second electrodes connecting the plurality of second electrode drivers to the memory cells. ### Claim 6 (depends on 1) The method of claim 1, wherein forming the memory array includes forming an array of phase change memory cells. ### Claim 7 (depends on 6) The method of claim 6, wherein forming the memory array includes forming a multi-deck array of phase change memory cells. ### Claim 8 A memory system, comprising: processing circuitry, wherein the processing circuitry is configured to cause the memory system to: form a memory array comprising a plurality of sub array regions across a footprint of the memory array; form a plurality of first electrode drivers distributed across the footprint of the memory array in a plurality of disjointed first electrode driver regions; and form a plurality of second electrode drivers of a same type as the plurality of first electrode drivers and distributed across the footprint in a plurality of disjointed second electrode driver regions such that the plurality of first electrode drivers are oriented in a first direction and the plurality of second electrode drivers are oriented in a second direction perpendicular to the first direction, such that at least a portion of one of the plurality of disjointed first electrode driver regions and at least a portion of one of the plurality of disjointed second electrode driver regions are within each sub array region of the plurality of sub array regions, wherein each disjointed first electrode driver region of the plurality of disjointed first electrode driver regions within each sub array region spans less than a length of each corresponding sub array region. ### Claim 9 (depends on 8) The memory system of claim 8, wherein, to form the plurality of first electrode drivers in the plurality of disjointed first electrode driver regions, the processing circuitry is further configured to cause the memory system to: arrange first electrode driver regions of the plurality of disjointed first electrode driver regions in a repeating pattern of sub array regions across the footprint. ### Claim 10 (depends on 9) The memory system of claim 9, wherein to form the plurality of second electrode drivers, the processing circuitry is further configured to cause the memory system to: arrange the plurality of disjointed second electrode driver regions in the repeating pattern of sub array regions. ### Claim 11 (depends on 10) The memory system of claim 10, wherein, to arrange the plurality of disjointed first electrode driver regions and the plurality of disjointed second electrode driver regions in the repeating pattern, the processing circuitry is further configured to cause the memory system to: alternate the plurality of disjointed first electrode driver regions with the plurality of disjointed second electrode driver regions in at least one of a first electrode lengthwise direction and a second electrode lengthwise direction. ### Claim 12 (depends on 10) The memory system of claim 10, wherein, to form the memory array comprises forming staggered first electrodes connecting the plurality of first electrode drivers to memory cells of the memory array, the processing circuitry is further configured to cause the memory system to: form staggered second electrodes connecting the plurality of second electrode drivers to the memory cells. ### Claim 13 (depends on 8) The memory system of claim 8, wherein, to form the memory array, the processing circuitry is further configured to cause the memory system to: form an array of phase change memory cells. ### Claim 14 (depends on 13) The memory system of claim 13, wherein, to form the memory array, the processing circuitry is further configured to cause the memory system to: form a multi-deck array of phase change memory cells. ### Claim 15 A memory device, comprising: a memory array comprising a plurality of sub array regions across a footprint of the memory array; a plurality of first electrode drivers distributed across the footprint of the memory array in a plurality of disjointed first electrode driver regions; and a plurality of second electrode drivers of a same type as the plurality of first electrode drivers and distributed across the footprint in a plurality of disjointed second electrode driver regions such that the plurality of first electrode drivers are oriented in a first direction and the plurality of second electrode drivers are oriented in a second direction perpendicular to the first direction, such that at least a portion of one of the plurality of disjointed first electrode driver regions and at least a portion of one of the plurality of disjointed second electrode driver regions are within each sub array region of the plurality of sub array regions, wherein each disjointed first electrode driver region of the plurality of disjointed first electrode driver regions within each sub array region spans less than a length of each corresponding sub array region. ### Claim 16 (depends on 15) The memory device of claim 15, wherein first electrode driver regions of the plurality of disjointed first electrode driver regions are arranged in a repeating pattern of sub array regions across the footprint. ### Claim 17 (depends on 16) The memory device of claim 16, wherein the plurality of disjointed second electrode driver regions are arranged in the repeating pattern of sub array regions. ### Claim 18 (depends on 17) The memory device of claim 17, wherein the plurality of disjointed first electrode driver regions and the plurality of disjointed second electrode driver regions in the repeating pattern arrangement includes the plurality of disjointed first electrode driver regions alternated with the plurality of disjointed second electrode driver regions in at least one of a first electrode lengthwise direction and a second electrode lengthwise direction.