# US 12,119,054 B2 · Lifetime mixed level non-volatile memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,054 B2 - Document ID: US12119054B2 - Status: Granted - Kind: B2 - Application number: 18/613,466 - Filed: 2024-03-22 - Published: 2024-07-11 - Granted: 2024-10-15 - Earliest claimed: 2011-07-19 - Assignees: Vervain, LLC - Applicants: Vervain, LLC - Inventors: G. R. Mohan Rao - Web page: https://patentgrep.com/patent/US12119054B2 ## CPC - G11C 11/5635: {Erasing circuits} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 11/1072: {in multilevel memories} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G11C 11/5621: {using charge storage in a floating gate} - G11C 11/5678: {using amorphous/crystalline phase transition storage elements} - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 29/76: {using address translation or modifications} - G06F 2212/7202: Allocation control and policies - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A controller for managing at least one MLC non-volatile memory space including at least one MLC non-volatile memory element and at least one SLC non-volatile memory space including at least one SLC non-volatile memory element. The controller is adapted to determine if a range of addresses listed by an entry and mapped to the at least one MLC non-volatile memory element fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC memory element as stored data. In the event of such a failure, the controller remaps said entry to an the at least one SLC non-volatile memory element. ## Claims ### Claim 1 A system for storing data comprising: an MLC non-volatile memory space including at least one MLC non-volatile memory element; an SLC non-volatile memory module space including at least one SLC non-volatile memory element; a controller coupled to the at least one MLC non-volatile memory element and the at least one SLC non-volatile memory element wherein the controller is adapted to: a) maintain an address map of the MLC and SLC non-volatile memory spaces, the address map comprising a list of logical address ranges accessible by a computer system, the computer system having at least one processor, the list of logical address ranges having a minimum quanta of addresses, wherein each entry in the list of logical address ranges maps to a similar range of physical addresses within either the at least one SLC non-volatile memory element or within the at least one MLC non-volatile memory element; and b) determine if a range of addresses listed by an entry and mapped to a similar range of physical addresses within the at least one MLC non-volatile memory element, fails a data integrity test performed at the controller during a read operation, reading stored data from the MLC non-volatile memory space containing the at least one MLC non-volatile memory element, and, in an event of such a failure, the controller remaps the entry to a next available equivalent range of physical addresses within the at least one SLC non-volatile memory element. ### Claim 2 (depends on 1) The system of claim 1, wherein the minimum quanta of addresses is equal to one block. ### Claim 3 (depends on 1) The system of claim 1, wherein the minimum quanta of addresses is equal to one page. ### Claim 4 (depends on 1) The system of claim 1, wherein the at least one MLC non-volatile memory element is NAND flash memory. ### Claim 5 (depends on 1) The system of claim 1, wherein the at least one SLC non-volatile memory element is NAND flash memory. ### Claim 6 (depends on 1) The system of claim 1, wherein the at least one MLC non-volatile memory element is resistive random-access memory (RRAM). ### Claim 7 (depends on 1) The system of claim 1, wherein the at least one SLC non-volatile memory element is resistive random-access memory (RRAM). ### Claim 8 (depends on 1) The system of claim 1, wherein the at least one MLC non-volatile memory element is phase change memory (PCM). ### Claim 9 (depends on 1) The system of claim 1, wherein the at least one SLC non-volatile memory element is phase change memory (PCM). ### Claim 10 (depends on 1) The system of claim 1, wherein the at least one SLC non-volatile memory element is magnetic random-access memory (MA-GRAM). ### Claim 11 (depends on 1) The system of claim 1, wherein the controller causes a transfer of content on a periodic basis to enhance data integrity. ### Claim 12 (depends on 1) The system of claim 1, wherein the at least one MLC non-volatile memory element and the at least one SLC non-volatile memory element comprise a block with physical addresses. ### Claim 13 (depends on 1) The system of claim 1, wherein the at least one MLC non-volatile memory element and the at least one SLC non-volatile memory element comprise a page with physical addresses. ### Claim 14 (depends on 1) The system of claim 1, wherein a transfer of the stored data from the at least one MLC non-volatile memory element to the at least one SLC non-volatile memory element is temporary. ### Claim 15 (depends on 1) The system of claim 1, wherein a transfer of the stored data from the at least one MLC non-volatile memory element to the at least one SLC non-volatile memory element is temporary until an MLC non-volatile memory element is available. ### Claim 16 (depends on 1) The system of claim 1, wherein operations of the controller enhance a lifetime of the at least one MLC non-volatile memory element and the at least one SLC non-volatile memory element. ### Claim 17 (depends on 1) The system of claim 1, wherein the controller determines during a write operation if the range of addresses listed by the entry and mapped to the similar range of physical addresses within the at least one MLC non-volatile memory element, fails the data integrity test. ### Claim 18 A method for storing data comprising: providing an MLC non-volatile memory space including at least one MLC non-volatile memory element; providing an SLC non-volatile memory space including at least one SLC non-volatile memory element; and maintaining, using a controller coupled to the at least one MLC non-volatile memory element and the at least one SLC non-volatile memory element, an address map of the MLC and SLC non-volatile memory spaces, the address map comprising a list of logical address ranges accessible by a computer system, the computer system having at least one processor, the list of logical address ranges having a minimum quanta of addresses, wherein each entry in the list of logical address ranges maps to a similar range of physical addresses within either the at least one SLC non-volatile memory element or within the at least one MLC non-volatile memory element; determining, using the controller, if a range of addresses listed by an entry and mapped to a similar range of physical addresses within the at least one MLC non-volatile memory element, fails a data integrity test performed at the controller during a data read operation from the at least one MLC non-volatile memory element in the MLC non-volatile memory space; in an event of such a failure, remapping, using the controller, the entry to a next available equivalent range of physical addresses within the at least one SLC non-volatile memory element; and transferring the stored data from the at least one MLC non-volatile memory element to the at least one SLC non-volatile memory element using the controller. ### Claim 19 A system for storing data comprising: an MLC non-volatile memory space including at least one MLC non-volatile memory element; an SLC non-volatile memory module space including at least one SLC non-volatile memory element; a controller coupled to the at least one MLC non-volatile memory element and the at least one SLC non-volatile memory element wherein the controller is adapted to: a) maintain an address map of the MLC and SLC non-volatile memory spaces, the address map comprising a list of logical address ranges accessible by a computer system, the computer system having at least one processor, the list of logical address ranges having a minimum quanta of addresses, wherein each entry in the list of logical address ranges maps to a similar range of physical addresses within either the at least one SLC non-volatile memory element or within the at least one MLC non-volatile memory element; and b) determine if a range of addresses listed by an entry and mapped to a similar range of physical addresses within the at least one MLC non-volatile memory element, fails a data integrity test performed at the controller during a read-modify-write operation, reading stored data from the MLC non-volatile memory space containing the at least one MLC non-volatile memory element, and, in an event of such a failure, the controller remaps the entry to a next available equivalent range of physical addresses within the at least one SLC non-volatile memory element. ### Claim 20 A method for storing data comprising: providing an MLC non-volatile memory space including at least one MLC non-volatile memory element; providing an SLC non-volatile memory space including at least one SLC non-volatile memory element; and maintaining, using a controller coupled to the at least one MLC non-volatile memory element and the at least one SLC non-volatile memory element, an address map of the MLC and SLC non-volatile memory spaces, the address map comprising a list of logical address ranges accessible by a computer system, the list of logical address ranges having a minimum quanta of addresses, wherein each entry in the list of logical address ranges maps to a similar range of physical addresses within either the at least one SLC non-volatile memory element or within the at least one MLC non-volatile memory element; determining, using the controller, if a range of addresses listed by an entry and mapped to a similar range of physical addresses within the at least one MLC non-volatile memory element, fails a data integrity test performed at the controller during a read-modify-write operation from the at least one MLC non-volatile memory element in the MLC non-volatile memory space; in an event of such a failure, remapping, using the controller, the entry to a next available equivalent range of physical addresses within the at least one SLC non-volatile memory element; and transferring the stored data from the at least one MLC non-volatile memory element to the at least one SLC non-volatile memory element using the controller.