# US 12,119,053 B2 · Method of programming MLC memory device and related MLC memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,053 B2
- Document ID: US12119053B2
- Status: Granted
- Kind: B2
- Application number: 17/680,264
- Filed: 2022-02-24
- Published: 2023-07-27
- Granted: 2024-10-15
- Earliest claimed: 2022-01-21
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chia-Wen Wang; Chien-Hung Chen; Chia-Hui Huang; Jen-Yang Hsueh; Ling-Hsiu Chou; Chih-Yang Hsu
- Web page: https://patentgrep.com/patent/US12119053B2

## CPC

- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/10: Programming or data input circuits
- G11C 16/20: Initialising; Data preset; Chip identification
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

## Claims

### Claim 1

A method of programing a multi-level cell (MLC) memory device, comprising:
measuring a disturb characteristic of a program block in the MLC memory device, wherein the program block includes a plurality of memory cells, the disturb characteristic of a first memory cell in the program block is associated with an inter-cell interference between the first memory cell and at least a second memory cell in the program block during a programming operation, and the first memory cell and the second memory cell are neighboring memory cells in the program block;
acquiring threshold voltage variations of the plurality of memory cells according to the disturb characteristic of the program block;
determining P initial program voltage pulses associated with a predetermined signal level, wherein:
a level of an pth initial program voltage among the P initial program voltages is equal to a sum of an initial program voltage value and p times a unit voltage increment;
P is an integer larger than 1; and
p is a positive integer not larger than P;
providing P compensated program voltage pulses by adjusting the P initial program voltage pulses according to the threshold voltage variations of the plurality of memory cells, wherein a level of an pth compensated program voltage among the P compensated program voltages is equal to a sum of the initial program voltage value, p times the unit voltage increment and a threshold voltage variation of the plurality of memory cells when programed to the predetermined signal level; and
programming the plurality of memory cells to the predetermined signal level by outputting the plurality of compensated program voltage pulses to the program block.

### Claim 2 (depends on 1)

The method of claim 1, wherein a control end of each memory cell is coupled to a same word line in the MLC memory device.

### Claim 3 (depends on 2)

The method of claim 2, wherein the disturb characteristics of the program block are determined based on a predetermined program distribution of the memory cells coupled to each word line.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
providing the P compensated program voltage pulses by adjusting peak values of the P initial program voltage pulses according to the threshold voltage variations of the plurality of memory cells.

### Claim 5 (depends on 1)

The method of claim 1, wherein:
the P initial program voltage pulses include a 1st initial program voltage pulse to a pth initial program voltage pulse;
the P compensated program voltage pulses include a 1st compensated program voltage pulse to a Pth compensated program voltage pulse corresponding to the 1st initial program voltage pulse to the pth initial program voltage pulse, respectively;
peak values of the 1st initial program voltage pulse to the Pth initial program voltage pulse increase sequentially; and
peak values of the 1st compensated program voltage pulse to the pth compensated program voltage pulse increase sequentially; and
P is an integer larger than 1.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
programming the plurality of memory cells to the predetermined signal level by sequentially outputting the 1st compensated program voltage pulse to the pth compensated program voltage pulses to the program block.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
outputting a plurality of verify voltage pulses to the program block for verifying whether the plurality of memory cells have been programmed to the predetermined signal level.

### Claim 8

A multi-level cell (MLC) memory device, comprising:
a memory array comprising M columns and N rows of memory cells, wherein M and N are integers larger than 1; and
a processing circuit configured to:
acquire threshold voltage variations of each row of memory cells among the N rows of memory cells according to a disturb characteristic of each row of memory cells, wherein the disturb characteristic of a first memory cell in the memory array is associated with an inter-cell interference between the first memory cell and at least a second memory cell in the memory array during a programming operation, and the first memory cell and the second memory cell are neighboring memory cells in the memory array;
determine P initial program voltage pulses associated with a predetermined signal level for an operation to program an nth row of memory cells among the N rows of memory cells to the predetermined signal level, wherein n is a positive integer not larger than N;
provide P compensated program voltage pulses by adjusting the P initial program voltage pulses according to the threshold voltage variation of the nth row of memory cells; and
program the nth row of memory cells to the predetermined signal level by outputting the plurality of compensated program voltage pulses to the nth row of memory cells, wherein:
a level of an pth initial program voltage among the P initial program voltages is equal to a sum of an initial program voltage value and p times a unit voltage increment;
a level of an pth compensated program voltage among the P compensated program voltages is equal to a sum of the initial program voltage value, p times the unit voltage increment and a threshold voltage variation of the plurality of memory cells when programed to the predetermined signal level;
P is an integer larger than 1; and
p is a positive integer not larger than P.

### Claim 9 (depends on 8)

The MLC memory device of claim 8, wherein the processing circuit is further configured to:
provide the P compensated program voltage pulses by adjusting peak values of the P initial program voltage pulses according to the threshold voltage variations of the nth row of memory cells.

### Claim 10 (depends on 8)

The MLC memory device of claim 8, wherein the processing circuit is further configured to:
adjust the P compensated program voltage pulses based on a predetermined program distribution of each row of memory cells among the N rows of memory cells.

### Claim 11 (depends on 8)

The MLC memory device of claim 8, wherein:
the P initial program voltage pulses include a 1st initial program voltage pulse to a pth initial program voltage pulse;
the P compensated program voltage pulses include a 1st compensated program voltage pulse to a pth compensated program voltage pulse corresponding to the 1st initial program voltage pulse to the pth initial program voltage pulse, respectively;
peak values of the 1st initial program voltage pulse to the Pth initial program voltage pulse increase sequentially; and
peak values of the 1st compensated program voltage pulse to the pth compensated program voltage pulse increase sequentially.

### Claim 12 (depends on 8)

The MLC memory device of claim 8, wherein the processing circuit is further configured to:
program the nth row of memory cells to the predetermined signal level by sequentially outputting the 1st compensated program voltage pulse to the pth compensated program voltage pulses to the nth row of memory cells.

### Claim 13 (depends on 8)

The MLC memory device of claim 8, wherein the processing circuit is further configured to:
output a plurality of verify voltage pulses to the nth row of memory cells for verifying whether the nth row of memory cells have been programmed to the predetermined signal level.