# US 12,119,051 B2 · Memory array reset read operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,051 B2 - Document ID: US12119051B2 - Status: Granted - Kind: B2 - Application number: 17/884,861 - Filed: 2022-08-10 - Published: 2022-12-01 - Granted: 2024-10-15 - Earliest claimed: 2017-08-28 - Applicants: Micron Technology, Inc. - Inventors: Jeremy Binfet; Mark Helm; William Filipiak; Mark Hawes - Web page: https://patentgrep.com/patent/US12119051B2 ## CPC - G11C 11/419: Read-write [R-W] circuits - G11C 7/08: Control thereof - G11C 7/1015: {Read-write modes for single port memories, i.e. having either a random port or a serial port} - G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories} - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G11C 7/227: {Timing of memory operations based on dummy memory elements or replica circuits} - G11C 16/20: Initialising; Data preset; Chip identification - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2207/2281: Timing of a read operation - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input. ## Claims ### Claim 1 An apparatus, comprising: a memory device; and a controller coupled with the memory device and configured to cause the apparatus to: identify a command to perform a reset read operation for setting at least one portion of a memory array to a transient state; identify the at least one portion of the memory array based at least in part on the command; and execute the reset read operation on the at least one portion of the memory array based at least in part on identifying the at least one portion of the memory array, wherein executing the reset read operation comprises performing a read recovery part of a read operation, and wherein the transient state of memory cells of the at least one portion of the memory array that includes retaining a word line to a channel potential difference of the memory cells at a level that is lower than a voltage of a source, a drain, a bit line, or a combination thereof of the memory cells after executing the reset read operation. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the read operation comprises the read recovery part and a data sense part, and wherein the read recovery part of the read operation sets the at least one portion of the memory array to the transient state. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the controller is configured to cause the apparatus to: increase a voltage applied to one or more word lines associated with the at least one portion of the memory array to a transient voltage above a threshold voltage of memory cells of the at least one portion of the memory array; increase a voltage applied to at least one gate of at least one select gate device of the at least one portion of the memory array to a second voltage above a second threshold voltage of the at least one select gate device; and set a voltage applied to a source, a drain, a bit line, or a combination thereof, of the at least one portion of the memory array to a third voltage. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the controller is configured to cause the apparatus to: decrease the voltage applied to the one or more word lines from the transient voltage to a fourth voltage based at least in part on achieving the transient voltage; and decrease the voltage applied to the at least one gate of the at least one select gate device from the second voltage to below the second threshold voltage based at least in part on decreasing the voltage applied to the one or more word lines. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the controller is configured to cause the apparatus to: determine a duration since a last read operation for the at least one portion of the memory array, wherein identifying the at least one portion of the memory array is based at least in part on determining the duration. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the at least one portion of the memory array corresponds to a single block of the memory array. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the controller is configured to cause the apparatus to: determine a mode of executing the reset read operation, wherein executing the reset read operation is based at least in part on determining the mode. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the controller is configured to cause the apparatus to: identify a product design identification of the memory array, wherein determining the mode comprises determining a quantity of portions of the memory array on which the reset read operation is to be executed based at least in part on the product design identification. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the controller is configured to cause the apparatus to: execute the reset read operation concurrently on a plurality of portions of the memory array based at least in part on determining the quantity of portions. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the plurality of portions comprises a total quantity of blocks of the memory array. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the memory array comprises: at least one three-dimensional Not-AND (NAND) memory cell. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the controller is configured to cause the apparatus to: receive a request to perform the reset read operation; and initiate the reset read operation based at least in part on receiving the request. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the controller is configured to cause the apparatus to: identify a set feature and a trim condition associated with the reset read operation; and determine a configuration for executing the reset read operation based at least in part on identifying the set feature and the trim condition, wherein executing the reset read operation is based at least in part on determining the configuration. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the set feature and the trim condition comprise an execution of the reset read operation on a single block. ### Claim 15 (depends on 13) The apparatus of claim 13, wherein the set feature and the trim condition comprises an execution of the reset read operation on a maximum quantity of blocks defined by the trim condition. ### Claim 16 (depends on 13) The apparatus of claim 13, wherein the set feature and the trim condition comprise an automatic execution of the reset read operation. ### Claim 17 A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to: identify a command to perform a reset read operation for setting at least one portion of a memory array into a transient first state; identify the at least one portion of the memory array based at least in part on the part on the command; and execute the reset read operation on the at least one portion of the memory array based at least in part on identifying the at least one portion of the memory array, wherein executing the reset read operation comprises performing a read recovery part of a read operation, and wherein the transient state of memory cells of the at least one portion of the memory array that includes retaining a word line to a channel potential difference of the memory cells at a level that is lower than a voltage of a source, a drain, a bit line, or a combination thereof of the memory cells after execution of the reset read operation. ### Claim 18 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: determine a quantity of portions of the memory array on which the reset read operation is to be executed concurrently based at least in part on a product design identification of the memory array, wherein executing the command to perform the reset read operation is based at least in part on determining the quantity of portions of the memory array. ### Claim 19 A method, comprising: identifying a command to perform a reset read operation for setting at least one portion of a memory array into a transient state; identifying the at least one portion of the memory array based at least in part on the part on the command; and executing the reset read operation on the at least one portion of the memory array based at least in part on identifying the at least one portion of the memory array, wherein executing the reset read operation comprises performing a read recovery part of a read operation, and wherein the transient state of memory cells of the at least one portion of the memory array that includes retaining a word line to a channel potential difference of the memory cells at a level that is lower than a voltage of a source, a drain, a bit line, or a combination thereof of the memory cells after execution of the reset read operation. ### Claim 20 (depends on 19) The method of claim 19, further comprising: determining a quantity of portions of the memory array on which the reset read operation is to be executed concurrently based at least in part on a product design identification of the memory array, wherein executing the command to perform the reset read operation is based at least in part on determining the quantity of portions of the memory array.