# US 12,119,046 B2 · Nonvolatile memory device having multi-stack memory block and method of operating the same

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- Number: US 12,119,046 B2
- Document ID: US12119046B2
- Status: Granted
- Kind: B2
- Application number: 18/045,541
- Filed: 2022-10-11
- Published: 2023-05-11
- Granted: 2024-10-15
- Earliest claimed: 2021-11-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jaeduk Yu; Yohan Lee; Yonghyuk Choi; Jiho Cho
- Web page: https://patentgrep.com/patent/US12119046B2

## CPC

- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/20: Initialising; Data preset; Chip identification
- G11C 16/24: Bit-line control circuits
- G11C 16/32: Timing circuits
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 90/792: {between multiple chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A nonvolatile memory device having a multi-stack memory block includes: a memory cell array divided into a plurality of memory stacks disposed in a vertical direction; and a control circuit configured to perform a channel voltage equalization operation of the plurality of memory stacks, wherein inter-stack portions are between the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks. The control circuit determines, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and differently controls setup time points for applying a pass voltage, or recovery time points for applying a ground voltage, to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.

## Claims

### Claim 1

A nonvolatile memory device comprising:
a memory cell array comprising a plurality of cell strings in which a plurality of memory cells are disposed in a vertical direction, respectively, wherein the memory cell array is divided into a plurality of memory stacks disposed in the vertical direction, inter-stack portions are disposed between the plurality of memory stacks, word lines of the plurality of memory cells are stacked in the vertical direction in each of the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks; and
a control circuit configured to determine, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and perform a channel voltage equalization operation of the plurality of memory stacks while differently controlling setup time points for applying a pass voltage to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines,
wherein the pass voltage is set to a voltage by which the plurality of memory cells are turned on.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, wherein the control circuit is further configured to first set a first inter-stack word line among the inter-stack word lines having a larger channel hole and later set a second other inter-stack word line among the inter-stack word lines having a smaller channel hole when the inter-stack word lines are set to the pass voltage.

### Claim 3 (depends on 1)

The nonvolatile memory device of claim 1, wherein the control circuit is further configured to perform the channel voltage equalization operation of the plurality of memory stacks while differently controlling recovery time points for applying a recovery voltage to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.

### Claim 4 (depends on 3)

The nonvolatile memory device of claim 3, wherein the recovery voltage is set to a ground voltage, an external power source voltage applied to the nonvolatile memory device, or an internal power source voltage generated from the external power source voltage in the nonvolatile memory device.

### Claim 5 (depends on 3)

The nonvolatile memory device of claim 3, wherein the control circuit is further configured to first recover a first inter-stack word line among the inter-stack word lines having a smaller channel hole and later recover a second other inter-stack word line among the inter-stack word lines having a larger channel hole when the inter-stack word lines are recovered to the recovery voltage.

### Claim 6

A method of operating a nonvolatile memory device, the method comprising:
dividing, into a plurality of memory stacks, a memory cell array comprising a plurality of cell strings in which a plurality of memory cells are disposed in a vertical direction, respectively, wherein inter-stack portions are disposed between the plurality of memory stacks, word lines of the plurality of memory cells are stacked in the vertical direction in each of the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks;
determining, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks; and
performing a channel voltage equalization operation of the plurality of memory stacks while differently controlling setup time points for applying a pass voltage to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines,
wherein the pass voltage is set to a voltage by which the plurality of memory cells are turned on.

### Claim 7 (depends on 6)

The method of claim 6, further comprising storing, in the nonvolatile memory device, channel hole profile information indicating the some word lines in a manufacturing process step of the nonvolatile memory device.

### Claim 8 (depends on 7)

The method of claim 7, wherein the determining of the inter-stack word lines includes selecting some of the word lines adjacent to the inter-stack portions, based on the channel hole profile information.

### Claim 9 (depends on 6)

The method of claim 6, wherein the performing of the channel voltage equalization operation of the plurality of memory stacks further comprises first setting a first inter-stack word line among the inter-stack word lines, which has a larger channel hole, to the pass voltage and later setting a second other inter-stack word line among the inter-stack word lines, which has a smaller channel hole, to the pass voltage.

### Claim 10 (depends on 6)

The method of claim 6, wherein the plurality of memory stacks comprise a first memory stack, a second memory stack stacked on the first memory stack, and a first inter-stack portion disposed between the first memory stack and the second memory stack, and
the performing of the channel voltage equalization operation of the plurality of memory stacks further comprises:
setting a first inter-stack word line among the inter-stack word lines at a top of the first memory stack, which is adjacent to the first inter-stack portion, to the pass voltage at a first time point; and
setting a second inter-stack word line among the inter-stack word lines at a bottom of the second memory stack, which is adjacent to the first inter-stack portion, to the pass voltage at a second time point after the first time point.

### Claim 11 (depends on 10)

The method of claim 10, further comprising performing a program, a verify read, or a read operation on a selected cell string among the plurality of cell strings after the second time point.

### Claim 12 (depends on 6)

The method of claim 6, wherein the plurality of memory stacks comprise a first memory stack, a second memory stack stacked on the first memory stack, and a first inter-stack portion disposed between the first memory stack and the second memory stack, and
the performing of the channel voltage equalization operation of the plurality of memory stacks further comprises:
setting a first inter-stack word line among the inter-stack word lines at a top of the first memory stack, which is adjacent to the first inter-stack portion, to the pass voltage at a first time point;
setting a second inter-stack word line among the inter-stack word lines, which is beneath the first inter-stack word line, to the pass voltage at a second time point after the first time point;
setting a third inter-stack word line among the inter-stack word lines at a bottom of the second memory stack, which is adjacent to the first inter-stack portion, to the pass voltage at a third time point after the second time point; and
setting a fourth inter-stack word line among the inter-stack word lines, which is disposed on the third inter-stack word line, to the pass voltage at a fourth time point after the third time point.

### Claim 13 (depends on 12)

The method of claim 12, further comprising performing a program, a verify read, or a read operation on a selected cell string among the plurality of cell strings after the fourth time point.

### Claim 14

A method of operating a nonvolatile memory device, the method comprising:
dividing, into a plurality of memory stacks, a memory cell array comprising a plurality of cell strings in which a plurality of memory cells are disposed in a vertical direction, respectively, wherein inter-stack portions are disposed between the plurality of memory stacks, word lines of the plurality of memory cells are stacked in the vertical direction in each of the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks;
determining, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks; and
performing a channel voltage equalization operation of the plurality of memory stacks while differently controlling recovery time points for applying a recovery voltage to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.

### Claim 15 (depends on 14)

The method of claim 14, wherein the recovery voltage is set to a ground voltage, an external power source voltage applied to the nonvolatile memory device, or an internal power source voltage generated from the external power source voltage in the nonvolatile memory device.

### Claim 16 (depends on 14)

The method of claim 14, further comprising storing, in the nonvolatile memory device, channel hole profile information indicating the some word lines defined in a manufacturing process step of the nonvolatile memory device.

### Claim 17 (depends on 16)

The method of claim 16, wherein the determining of the inter-stack word lines includes selecting some of the word lines adjacent to the inter-stack portions, based on the channel hole profile information.

### Claim 18 (depends on 14)

The method of claim 14, wherein the performing of the channel voltage equalization operation of the plurality of memory stacks further comprises first recovering a first inter-stack word line among the inter-stack word lines, which has a smaller channel hole among the inter-stack word lines, to the recovery voltage and later recovering a second other inter-stack word line among the inter-stack word lines, which has a larger channel hole to the recovery voltage.

### Claim 19 (depends on 14)

The method of claim 14, wherein the plurality of memory stacks comprise a first memory stack, a second memory stack stacked on the first memory stack, and a first inter-stack portion disposed between the first memory stack and the second memory stack, and
the performing of the channel voltage equalization operation of the plurality of memory stacks further comprises:
recovering a second inter-stack word line among the inter-stack word lines at a bottom of the second memory stack, which is adjacent to the first inter-stack portion, to the recovery voltage at a first time point; and
recovering a first inter-stack word line among the inter-stack word lines at a top of the first memory stack, which is adjacent to the first inter-stack portion, to the recovery voltage at a second time point after the first time point.

### Claim 20 (depends on 14)

The method of claim 14, wherein the plurality of memory stacks comprise a first memory stack, a second memory stack stacked on the first memory stack, and a first inter-stack portion disposed between the first memory stack and the second memory stack, and
the performing of the channel voltage equalization operation of the plurality of memory stacks further comprises:
recovering a second inter-stack word line among the inter-stack word lines, which is beneath a first inter-stack word line among the inter-stack word lines at a top of the first memory stack, to the recovery voltage at a first time point, the first inter-stack word line being adjacent to the first inter-stack portion;
recovering the first inter-stack word line to the recovery voltage at a second time point after the first time point;
recovering a fourth inter-stack word line among the inter-stack word lines, which is disposed on a third inter-stack word line among the inter-stack word lines at a bottom of the second memory stack, to the recovery voltage at a third time point after the second time point, the third inter-stack word line being adjacent to the first inter-stack portion; and
recovering the third inter-stack word line to the recovery voltage at a fourth time point after the third time point.