# US 12,118,964 B2 · Display controller and method having automatic data underrun recovery function

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- Number: US 12,118,964 B2
- Document ID: US12118964B2
- Status: Granted
- Kind: B2
- Application number: 17/768,494
- Filed: 2020-09-17
- Published: 2024-03-28
- Granted: 2024-10-15
- Earliest claimed: 2020-03-27
- Assignees: Nanjing SemiDrive Technology LTD.
- Applicants: Nanjing Semidrive Technology Co., Ltd.
- Inventors: Qiaoyu Ye
- Web page: https://patentgrep.com/patent/US12118964B2

## CPC

- G09G 5/39: Control of the bit-mapped memory
- G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)}
- G09G 3/36: using liquid crystals
- G09G 5/399: using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
- G09G 2340/00: Aspects of display data processing
- G09G 2350/00: Solving problems of bandwidth in display systems
- G09G 2360/18: Use of a frame buffer in a display terminal, inclusive of the display panel
- G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit
- G09G 2380/10: Automotive applications
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A display controller having an automatic data underrun recovery function, comprising: a direct memory access (DMA) controller coupled to an image data processor; the image data processor coupled to an image layer synthesizer; the image layer synthesizer coupled to a first-in first-out (FIFO) memory; a display timing generation circuit (DTC) coupled to the FIFO memory, the display timing generation circuit (DTC) being coupled to an external display device; and an underrun state machine separately coupled to the display timing generation circuit (DTC), an underload data counter, the DMA controller, the image data processor, the image layer synthesizer, and the FIFO memory. The provided display controller has an automatic data underrun recovery function.

## Claims

### Claim 1

A display controller with data under run self-recovery function, characterized in that, it comprises:
an image processor and a timing controller (TCON),
the image processor further comprises a direct memory access (DMA) controller, an image data processor, an image layer combiner, and a first-in-first-out (FIFO) memory;
the timing controller further comprises a display timing circuit (DTC), an under run state machine, and an under run data counter;
wherein the DMA controller is directly coupled to the image data processor, the image data processor is directly coupled to the image layer combiner, the image layer combiner is directly coupled to the FIFO memory, the DTC is directly coupled to the FIFO memory, the DTC is directly coupled to an external display device, and the under run state machine is directly coupled to each of the DTC, the under run data counter, the direct memory access DMA controller, the image data processor, the image layer combiner and the FIFO memory respectively,
wherein the display timing circuit DTC is configured to execute the following steps:
access the FIFO memory to acquire the image data stored in the FIFO memory;
according to the timing requirements of the external display device, generate four types of control signals required by th display device, including a frame synchronization signal (VSYNC), a line synchronization signal (HSYNC), a data enable signal (DE) and a display clock signal (PCLK);
when the DE is valid, continuously acquire the image display data from the FIFO memory, and send display data (PDATA) to the display device for display at the rising edge of each PCLK, wherein the under run state machine is configured to execute the following steps:
receive the VSYNC and the HSYNC sent by the DTC and a null value signal (FIFO_EMPTY) returned by the FIFO memory,
while the DE is valid, determine if the FIFO_EMPTY returned by the FIFO memory is valid; a valid FIFO_EMPTY being indicative that the timing controller TCON bas encountered a data under run problem when reading the FIFO memory;
then the under run state machine jumping first under run state, and
wherein when the under run state machine is in the first under run state, the under run state machine is configured to execute the following steps:
send a count increment instruction to the under run data counter if the FIFO_EMPTY is valid and a FIFO read request signal is valid;
according to a value of under run data logged by the under run data counter when the DE is invalid in a line blanking or a frame blanking region, send a FIFO read request instruction to the FIFO memory to read data, the number of which is equal to the value of under run data; send a count decrement instruction from the under run statement to the under run data counter whenever a data item is read,
the under run state machine exits the first under run state and moves to a normal state when the under run data counter is zero.

### Claim 2 (depends on 1)

The display controller according to claim 1, characterized in that, the under run state machine is configured to execute the following steps:
determine whether the count value of the under run data counter is zero when the VSYNC is valid;
the under run state machine moves from the first under run state to a second under run state when the count value of the under run data counter is zero.

### Claim 3 (depends on 2)

The display controller according to claim 2, characterized in that, when the under run state machine is in the second under run state, the under run state machine is configured to execute the following steps:
use a software-programmable register as a switch, and generate a clear signal (TCON_FLUSH) when the register is switched on;
clear the residual data in the entire pipeline by means of the TCON_FLUSH;
when the register is switched off, the under run state machine exits the second under run state and moves to the first under run state, and continues execution of all processes in the first under run state.

### Claim 4

A display control method with data under run self-recovery function, characterized in that, said method comprises:
display control by an image processor and a timing controller (TCON),
wherein the image processor further comprises a direct memory access (DMA); controller, an image data processor, an image layer combiner, and a first-in-first-out (FIFO, memory;
wherein DMA controller is directly coupled to the image data processor, the image data processor is directly coupled to the image layer combiner, the image layer combiner is directly coupled to the FIFO memory, the DTC is directly coupled to the FIFO memory, the DTC is directly coupled to an external display device, and the under run state machine is directly coupled to each of the DTC, the under run data counter, the direct memory access DMA controller, the image layer combiner and the FIFO memory respectively,
the DTC is configured to perform the steps of:
accessing the FIFO memory, to acquire the image data stored in the FIFO memory;
the DTC receiving a display trigger signal from the external display device and generating four types of control signals according to the image data stored in the FIFO memory, including a frame synchronization signal VSYNC, a data enable signal (DE), a line synchronization signal (HSYNC) and a display clock signal (PCLK);
the DTC converting the image data into display data (PDATA), according to the VSYNC and the HSYNC;
when the DE is valid, the DTC sending the PDATA to the external display device for image display according to the PCLK;
the DTC sending the VSYNC and HSYNC and receiving an FIFO empty signal (FIFO_EMPTY) from the FIFO memory;
while the DE remains valid, determining by the DTC if the FIFO_EMPTY is valid to indicate that the TCON has encountered a data under run problem when reading the FIFO memory;
determining by the DTC that a data under run problem in the first state or the second sate has occurred through comparison between the data under run time length and a preset time length value;
the DTC carrying out corresponding under run processing according to the judgment result,
wherein, the under run state machine executes the following steps when the DTC determines a first under run state;
the under run state machine sends a count increment instruction to the under run data counter if the FIFO_EMPTY is valid and a FIFO read request is valid,
according to the value of the under run data logged by the under run data counter, when the DE is invalid in a line blanking or frame blanking region, the under run state machine sends a FIFO read request instruction to the FIFO memory to read data equal to the value of the under run data,
the under run state machine sending a count decrement instruction to the under run data counter whenever a data item is read,
the under state machine exiting the first run state and moving to a normal state when the under run counter is zero.

### Claim 5 (depends on 1)

The display control method according to claim 1, characterized in that, the following steps are performed: determining whether the count value of the under run data counter is zero when the VSYNC is valid; the under run state machine moving from the first under run state to a second under run state once the count value of the under run data counter is zero.

### Claim 6 (depends on 5)

The display control method according to claim 5, characterized in that, the under run state machine executes the following steps when it is in the second under run state:
using a software-programmable register as a switch, and generating a clear signal (TCON_FLUSH) when the register is switched on;
clearing the residual data in the entire pipeline by means of the clearing signal (TCON_FLUSH);
when the register is switched off, the under run state machine exiting the second under run state and moving to the first under run state, and continuing execution of all processes in the first under run state.