# US 12,118,956 B2 · Display panel control method and display module

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- Number: US 12,118,956 B2
- Document ID: US12118956B2
- Status: Granted
- Kind: B2
- Application number: 17/758,977
- Filed: 2022-06-16
- Published: 2024-06-13
- Granted: 2024-10-15
- Earliest claimed: 2022-05-26
- Assignees: Tcl China Star Optoelectronics Technology Co., Ltd.
- Applicants: Huizhou China Star Optoelectronics Display Co., Ltd.; Tcl China Star Optoelectronics Technology Co., Ltd.
- Inventors: Ruiming Huang
- Web page: https://patentgrep.com/patent/US12118956B2

## CPC

- G09G 3/3696: {Generation of voltages supplied to electrode drivers}
- G09G 3/36: using liquid crystals
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G09G 3/3655: {Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors}
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2320/0219: Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
- G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
- G09G 2320/0257: Reduction of after-image effects
- G09G 2330/021: Power management, e.g. power saving
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present application provides a display panel control method and a display module. A display voltage corresponding to corresponding pixel unit can be compensated for based on a difference between a first feed-through voltage generated by a pixel electrode when a first transistor is turned from on to off and a second feed-through voltage generated by a common electrode when a second transistor is turned from on to off, so as to improve the problem such as the flicker or the image sticking in the display picture due to the unevenness of the feed-through voltages.

## Claims

### Claim 1

A display panel control method, wherein, the display panel comprises a plurality of data lines, a plurality of common lines, and a plurality of pixel units, wherein each of the pixel units comprises a first transistor, a second transistor, a pixel electrode, and a common electrode, wherein a source and a drain of the first transistor are electrically connected between the pixel electrode and the data line, and a source and a drain of the second transistor are electrically connected between the common electrode and the common line; the pixel electrode generates a first feed-through voltage when the first transistor is changed from an on state to an off state; and the common electrode generates a second feed-through voltage when the second transistor is changed from the on state to the off state; wherein the control method comprises:
compensating for a display voltage corresponding to each of the plurality of pixel units based on a difference between the first feed-through voltage and the second feed-through voltage of the pixel unit, comprising:
compensating for a data voltage transmitted by the data line or a common voltage transmitted by the common line corresponding to each of the plurality of pixel units based on each of a plurality of first differences between the first feed-through voltage and the second feed-through voltage of each of the plurality of pixel units.

### Claim 2 (depends on 1)

The control method of claim 1, wherein before compensating for a data voltage transmitted by the data line or a common voltage transmitted by the common line corresponding to each of the plurality of pixel units based on each of a plurality of first differences between the first feed-through voltage and the second feed-through voltage of each of the plurality of pixel units, further comprising:
acquiring the first feed-through voltages and the second feed-through voltages corresponding to the plurality of pixel units; and
calculating the plurality of first differences between the first feed-through voltages and the second feed-through voltages of the plurality of pixel units.

### Claim 3 (depends on 2)

The control method of claim 2, wherein:
a calculation formula of the first feed-through voltage is: VFT1=CGD1/(Clc+Cst+CGD1+Csu)*ΔVG1;
a calculation formula of the second feed-through voltage is: VFT2=CGD2/(Clc+Cst+CGD2+Csu)*ΔVG2; and
a calculation formula of the first difference is: X=VFT1−VFT2;
wherein CGD1 represents a parasitic capacitance between a scanning line electrically connected to the first transistor and the pixel electrode, and CGD2 represents a parasitic capacitance between a scanning line electrically connected to the second transistor and the common electrode; ΔVG1 represents a voltage change amount on the scanning line electrically connected to the first transistor, and ΔVG2 represents a voltage change amount on the scanning line electrically connected to the second transistor; and Csu represents a sum of remaining of a plurality of parasitic capacitance generated between any two of the pixel electrode, the data line, the common line, the scanning line, and the common electrode other than CGD1 and CGD2.

### Claim 4

A display module, comprising a display panel and a driving module electrically connected to the display panel, wherein the display panel comprises:
a plurality of data lines;
a plurality of common lines; and
a plurality of pixel units, wherein each of the pixel units comprises a first transistor, a second transistor, a pixel electrode, and a common electrode, wherein a source and a drain of the first transistor are electrically connected between the pixel electrode and the data line, and a source and a drain of the second transistor are electrically connected between the common electrode and the common line; the pixel electrode generates a first feed-through voltage when the first transistor is changed from an on state to an off state; and the common electrode generates a second feed-through voltage when the second transistor is changed from the on state to the off state;
wherein the driving module is electrically connected to the plurality of data lines and the plurality of common lines, and configured to compensate for a display voltage corresponding to each of the plurality of pixel units based on a difference between the first feed-through voltage and the second feed-through voltage of the pixel unit;
wherein a first difference exists between the first feed-through voltage and the second feed-through voltage, and the driving module compensates for the display voltage corresponding to respective pixel unit of the plurality of pixel units based on the first difference of the pixel unit.

### Claim 5 (depends on 4)

The display panel of claim 4, wherein the driving module comprises a timing controller and a power management chip electrically connected to the timing controller, wherein the timing controller compensates for an output signal of the power management chip based on the first difference to compensate for the display voltage corresponding to respective pixel unit of the plurality of pixel units.

### Claim 6 (depends on 5)

The display panel of claim 5, wherein the display voltage comprises a data voltage, and the driving module further comprises a source driving chip electrically connected to both the power management chip and the plurality of data lines, wherein the source driving chip outputs a plurality of data voltage to the plurality of data lines based on the output signal of the power management chip.

### Claim 7 (depends on 6)

The display panel of claim 6, wherein a gray scale level corresponding to the display voltage before compensation is inversely proportional to the first difference.

### Claim 8 (depends on 6)

The display panel of claim 6, wherein each of the pixel units has a plurality of first difference when being corresponding to a plurality of gray scale levels, and the number of the first difference having different values is less than or equal to the number of gray scale levels of the display panel.

### Claim 9 (depends on 5)

The display panel of claim 5, wherein the display voltage comprises a common voltage, and the plurality of common lines are electrically connected to the power management chip, wherein the power management chip outputs a common voltage to each of the plurality of common lines.

### Claim 10 (depends on 9)

The display panel of claim 9, wherein the plurality of pixel units have a plurality of first differences when being corresponding to a plurality of gray scale levels, and the plurality of first differences have a first maximum difference and a first minimum difference;
wherein, the common voltage is equal to an average of the first maximum difference and the first minimum difference.

### Claim 11 (depends on 5)

The display panel of claim 5, wherein the timing controller comprises a storage module configured to store a plurality of first differences.

### Claim 12 (depends on 4)

The display panel of claim 4, wherein the pixel unit further comprises a liquid crystal capacitor, a storage capacitor, and a liquid crystal layer, wherein the liquid crystal capacitor is constituted by the pixel electrode, the common electrode, and the liquid crystal layer; the storage capacitor is connected in parallel with the liquid crystal capacitor, and the storage capacitor is connected in series between one of a source and a drain of the first transistor electrically connected to the pixel electrode and one of a source and a drain of the second transistor electrically connected to the common electrode.

### Claim 13 (depends on 12)

The display panel of claim 12, wherein both electrodes of the storage capacitor are constituted by a second common line and the pixel electrode, respectively.

### Claim 14 (depends on 13)

The display panel of claim 13, wherein the plurality of common lines comprise a plurality of first common lines and a plurality of second common lines, wherein the plurality of first common lines are disposed in parallel with and spaced apart from the scanning lines, and the plurality of second common lines are disposed in parallel with and spaced apart from the data lines.

### Claim 15 (depends on 4)

The display panel of claim 4, wherein the pixel unit further comprises a first capacitor and a second capacitor, wherein the first capacitor is connected in series between one of a source or a drain of the first transistor electrically connected to the pixel electrode and a first voltage terminal, and the second capacitor is connected in series between one of a source or a drain of the second transistor electrically connected to the common electrode and the first voltage terminal.

### Claim 16 (depends on 4)

The display panel of claim 4, wherein the display panel further comprises a plurality of scanning lines, wherein a gate of the first transistor and a gate of the second transistor of the same pixel unit are electrically connected to the same scanning line.