# US 12,118,948 B2 · Gate drive circuit, display panel, and display apparatus

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- Number: US 12,118,948 B2
- Document ID: US12118948B2
- Status: Granted
- Kind: B2
- Application number: 18/212,896
- Filed: 2023-06-22
- Published: 2024-09-12
- Granted: 2024-10-15
- Earliest claimed: 2023-03-10
- Assignees: Xiamen Tianma Display Technology Co., Ltd.
- Applicants: Xiamen Tianma Display Technology Co., Ltd.
- Inventors: Zhiwei Zhou; Wenxin Lin
- Web page: https://patentgrep.com/patent/US12118948B2

## CPC

- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3677: {suitable for active matrices only}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS

## Abstract

A gate drive circuit, a display panel and a display apparatus are provided in the present disclosure. The gate drive circuit includes a quantity n of shift register units arranged along a first direction. A shift register unit includes an input circuit, a first node control circuit, a second node control circuit and an output control circuit. The first node control circuit is configured to control a stage of a first node; and the second node control circuit is configured to control a stage of a second node. The output control circuit is configured to control the scan signal output terminal to output a scan signal. Control terminals of an input circuit of an m-th shift register unit are electrically connected to scan signal output terminals of an (m+1)-th shift register unit and an (m−1)-th shift register unit respectively, where m∈n.

## Claims

### Claim 1

A gate drive circuit, comprising:
a quantity n of shift register units arranged along a first direction, wherein:
a shift register unit includes an input circuit, a first node control circuit, a second node control circuit and an output control circuit, wherein each of the input circuit, the first node control circuit and the second node control circuit is electrically connected to a third node; the first node control circuit is configured to control a stage of a first node; the second node control circuit is configured to control a stage of a second node; the output control circuit is electrically connected to each of a scan signal output terminal, the first node and the second node, and configured to control the scan signal output terminal to output a scan signal according to the stage of the first node and the stage of the second node;
along the first direction, control terminals of an input circuit of an m-th shift register unit are electrically connected to a scan signal output terminal of an (m+1)-th shift register unit and a scan signal output terminal of an (m−1)-th shift register unit respectively, wherein m∈n;
the input circuit includes a first input selection unit and a second input selection unit; the first input selection unit includes a first input terminal, a first output terminal and a first control terminal; and the second input selection unit includes a second input terminal, a second output terminal and a second control terminal;
the first input terminal is electrically connected to a first signal line, and the first output terminal is electrically connected to the third node;
the second input terminal is electrically connected to a second signal line, and the second output terminal is electrically connected to the third node; and
along the first direction, a first control terminal of the m-th shift register unit is electrically connected to the scan signal output terminal of the (m+1)-th shift register unit; and a second control terminal of the m-th shift register unit is electrically connected to the scan signal output terminal of the (m−1)-th shift register unit; and
when the gate drive circuit operates in a forward direction scan mode, the first signal line transmits a high-level signal, and the second signal line transmits a low-level signal.

### Claim 2 (depends on 1)

The gate drive circuit according to claim 1, wherein:
along the first direction, a control terminal of an input circuit in a first shift register unit is electrically connected to a start transmission signal line; and a control terminal of an input circuit of an n-th shift register unit is electrically connected to the start transmission signal line.

### Claim 3 (depends on 1)

The gate drive circuit according to claim 1, wherein:
when being operated in the forward direction scan mode, the gate drive circuit includes a first period and a second period;
at the first period, in the m-th shift register unit, the second control terminal is turned on in response to an enable signal outputted from the scan signal output terminal of the (m−1)-th shift register unit, and the first control terminal is turned off in response to the disenable signal outputted from the scan signal output terminal of the (m+1)-th shift register unit, such that the low-level signal is written into the first node; and
at the second period, in the m-th shift register unit, the second control terminal is turned off in response to the disenable signal outputted from the scan signal output terminal of the (m−1)-th shift register unit, and the first control terminal is turned on in response to the enable signal outputted from the scan signal output terminal of the (m+1)-th shift register unit, such that the high-level signal is written into the first node.

### Claim 4 (depends on 1)

The gate drive circuit according to claim 1, wherein:
when the gate drive circuit operates in a reverse direction scan mode, the first signal line transmits a low-level signal, and the second signal line transmits a high-level signal.

### Claim 5 (depends on 4)

The gate drive circuit according to claim 4, wherein:
when being operated in the reverse direction scan mode, the gate drive circuit includes a first period and a second period;
at the first period, in the m-th shift register unit, the first control terminal is turned on in response to the enable signal outputted from the scan signal output terminal of the (m+1)-th shift register unit, and the second control terminal is turned off in response to the disenable signal outputted from the scan signal output terminal of the (m−1)-th shift register unit, such that the low-level signal is written into the first node; and
at the second period, in the m-th shift register unit, the first control terminal is turned off in response to the disenable signal outputted from the scan signal output terminal of the (m+1)-th shift register unit, and the second control terminal is turned on in response to the enable signal outputted from the scan signal output terminal of the (m−1)-th shift register unit, such that the high-level signal is written into the first node.

### Claim 6 (depends on 1)

The gate drive circuit according to claim 1, wherein:
the first input selection unit includes a first switch, wherein an input terminal of the first switch is the first input terminal, an output terminal of the first switch is the first output terminal, and a control terminal of the first switch is the first control terminal; and
the second input selection unit includes a second switch, wherein an input terminal of the second switch is the second input terminal, an output terminal of the second switch is the second output terminal, and a control terminal of the second switch is the second control terminal.

### Claim 7

A display panel, comprising:
a gate drive circuit, comprising:
a quantity n of shift register units arranged along a first direction, wherein:
a shift register unit includes an input circuit, a first node control circuit, a second node control circuit and an output control circuit, wherein each of the input circuit, the first node control circuit and the second node control circuit is electrically connected to a third node; the first node control circuit is configured to control a stage of a first node; the second node control circuit is configured to control a stage of a second node; the output control circuit is electrically connected to each of a scan signal output terminal, the first node and the second node, and configured to control the scan signal output terminal to output a scan signal according to the stage of the first node and the stage of the second node;
along the first direction, control terminals of an input circuit of an m-th shift register unit are electrically connected to a scan signal output terminal of an (m+1)-th shift register unit and a scan signal output terminal of an (m−1)-th shift register unit respectively, wherein m∈n; and
the display panel further includes a plurality of forward and reverse direction scan selection circuits and a plurality of pixel rows, wherein:
a pixel row of the plurality of pixel rows includes a plurality of sub-pixels, and a sub-pixel of the plurality of sub-pixels includes a pixel circuit and a light-emitting element;
one forward and reverse direction scan selection circuit is electrically connected to at least one pixel circuit;
a forward and reverse direction scan selection circuit of the plurality of forward and reverse direction scan selection circuits includes a forward and reverse direction scan selection output terminal and a forward and reverse direction scan selection input terminal;
the forward and reverse direction scan selection output terminal of the forward and reverse direction scan selection circuit is electrically connected to the pixel circuit; and
along the first direction, both the scan signal output terminal of the (m+1)-th shift register unit and the scan signal output terminal of the (m−1)-th shift register unit are electrically connected to the forward and reverse direction scan selection input terminal of the forward and reverse direction scan selection circuit.

### Claim 8 (depends on 7)

The display panel according to claim 7, wherein:
the forward and reverse direction scan selection circuit includes a first scan selection unit and a second scan selection unit; the first scan selection unit includes a first scan input terminal, a first scan control terminal and a first scan output terminal; the second scan selection unit includes a second scan input terminal, a second scan control terminal and a second scan output terminal; forward and reverse direction scan selection output terminals include a first scan output terminal and a second scan output terminal; the first scan output terminal is electrically connected to the second scan output terminal; and forward and reverse direction scan selection input terminals include a first scan input terminal and a second scan input terminal;
along the first direction, the scan signal output terminal of the (m−1)-th shift register unit is electrically connected to the first scan input terminal, and the scan signal output terminal of the (m+1)-th shift register unit is electrically connected to the second scan input terminal;
the first scan control terminal is electrically connected to a first control signal line; and
the second scan control terminal is electrically connected to a second control signal line.

### Claim 9 (depends on 8)

The display panel according to claim 8, wherein:
the pixel circuit includes a drive transistor and a first initialization circuit;
an output terminal of the first initialization circuit is electrically connected to a control electrode of the drive transistor; and
a control terminal of the first initialization circuit is electrically connected to the first scan output terminal and the second scan output terminal.

### Claim 10 (depends on 9)

The display panel according to claim 9, wherein:
when the gate drive circuit operates in a forward direction scan mode, the first scan selection unit is turned on in response to an enable signal outputted from the first control signal line, and the second scan selection unit is turned off in response to a disenable signal outputted from the second control signal line; or
when the gate drive circuit operates in a reverse direction scan mode, the first scan selection unit is turned off in response to a disenable signal outputted from the first control signal line, and the second scan selection unit is turned on in response to an enable signal outputted from the second control signal line.

### Claim 11 (depends on 8)

The display panel according to claim 8, wherein:
the pixel circuit includes a drive transistor and a data write circuit;
an output terminal of the data write circuit is electrically connected to a first electrode of the drive transistor; and
a control terminal of the data write circuit is electrically connected to the first scan output terminal and the second scan output terminal.

### Claim 12 (depends on 11)

The display panel according to claim 11, wherein:
when the gate drive circuit operates in a forward direction scan mode, the first scan selection unit is turned off in response to a disenable signal outputted from the first control signal line, and the second scan selection unit is turned on in response to an enable signal outputted from the second control signal line; or
when the gate drive circuit operates in a reverse direction scan mode, the first scan selection unit is turned on in response to an enable signal outputted from the first control signal line, and the second scan selection unit is turned off in response to a disenable signal outputted from the second control signal line.

### Claim 13 (depends on 8)

The display panel according to claim 8, wherein:
the pixel circuit includes a drive transistor, a data write circuit and a threshold compensation circuit;
an output terminal of the data write circuit is electrically connected to a first electrode of the drive transistor;
a control terminal of the data write circuit is electrically connected to the first scan output terminal and the second scan output terminal;
an input terminal of the threshold compensation circuit is electrically connected to a second electrode of the drive transistor, and an output terminal of the threshold compensation circuit is electrically connected to a control terminal of the drive transistor; and
a control terminal of the threshold compensation circuit is electrically connected to the first scan output terminal and the second scan output terminal.

### Claim 14 (depends on 13)

The display panel according to claim 13, wherein:
when the gate drive circuit operates in a forward direction scan mode, the first scan selection unit is turned off in response to a disenable signal outputted from the first control signal line, and the second scan selection unit is turned on in response to an enable signal outputted from the second control signal line; or
when the gate drive circuit operates in a reverse direction scan mode, the first scan selection unit is turned on in response to an enable signal outputted from the first control signal line, and the second scan selection unit is turned off in response to a disenable signal outputted from the second control signal line.

### Claim 15 (depends on 8)

The display panel according to claim 8, wherein:
the first scan selection unit includes a first scan selection switch, wherein an input terminal of the first scan selection switch is the first scan input terminal, a control terminal of the first scan selection switch is the first scan control terminal, and an output terminal of the first scan selection switch is the first scan output terminal; and
the second scan selection unit includes a second scan selection switch, wherein an input terminal of the second scan selection switch is the second scan input terminal, a control terminal of the second scan selection switch is the second scan control terminal, and an output terminal of the second scan selection switch is the second scan output terminal.

### Claim 16 (depends on 7)

The display panel according to claim 7, wherein:
one forward and reverse direction scan selection circuit is electrically connected to one pixel row correspondingly; or
the plurality of forward and reverse direction scan selection circuits is electrically connected to the plurality of sub-pixels in a one-to-one correspondence.

### Claim 17

A display apparatus, comprising:
a display panel, comprising:
a gate drive circuit, comprising:
a quantity n of shift register units arranged along a first direction, wherein:
a shift register unit includes an input circuit, a first node control circuit, a second node control circuit and an output control circuit, wherein each of the input circuit, the first node control circuit and the second node control circuit is electrically connected to a third node; the first node control circuit is configured to control a stage of a first node; the second node control circuit is configured to control a stage of a second node; the output control circuit is electrically connected to each of a scan signal output terminal, the first node and the second node, and configured to control the scan signal output terminal to output a scan signal according to the stage of the first node and the stage of the second node; and
along the first direction, control terminals of an input circuit of an m-th shift register unit are electrically connected to a scan signal output terminal of an (m+1)-th shift register unit and a scan signal output terminal of an (m−1)-th shift register unit respectively, wherein m∈n;
the input circuit includes a first input selection unit and a second input selection unit; the first input selection unit includes a first input terminal, a first output terminal and a first control terminal; and the second input selection unit includes a second input terminal, a second output terminal and a second control terminal;
the first input terminal is electrically connected to a first signal line, and the first output terminal is electrically connected to the third node;
the second input terminal is electrically connected to a second signal line, and the second output terminal is electrically connected to the third node; and
along the first direction, a first control terminal of the m-th shift register unit is electrically connected to the scan signal output terminal of the (m+1)-th shift register unit; and a second control terminal of the m-th shift register unit is electrically connected to the scan signal output terminal of the (m−1)-th shift register unit; and
when the gate drive circuit operates in a forward direction scan mode, the first signal line transmits a high-level signal, and the second signal line transmits a low-level signal.