# US 12,118,947 B2 · Scanning line drive circuit and display device provided with same

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- Number: US 12,118,947 B2
- Document ID: US12118947B2
- Status: Granted
- Kind: B2
- Application number: 18/028,710
- Filed: 2020-10-02
- Published: 2023-10-19
- Granted: 2024-10-15
- Earliest claimed: 2020-10-02
- Assignees: Sharp Kabushiki Kaisha
- Applicants: Sharp Kabushiki Kaisha
- Inventors: Nobuyuki Taya; Makoto Yokoyama; Naoki Ueda
- Web page: https://patentgrep.com/patent/US12118947B2

## CPC

- G09G 3/3266: Details of drivers for scan electrodes
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G11C 19/287: {Organisation of a multiplicity of shift registers}
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/041: Temperature compensation
- G09G 2320/043: Preventing or counteracting the effects of ageing
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The scanning line drive circuit has a configuration in which a plurality of unit circuits are connected in multiple stages. A unit circuit includes: a first transistor having a first conductive terminal to which a first-level voltage is applied and a second conductive terminal connected to a first node; a second transistor having a second conductive terminal to which a second-level voltage is applied; a third transistor having a first conductive terminal connected to the first node and a second conductive terminal connected to a first conductive terminal of the second transistor; a fourth transistor having a first conductive terminal connected to a control terminal of the third transistor, and having a second conductive terminal and a control terminal to both of which the second-level voltage is applied; and an output transistor having a control terminal connected to the first node and a second conductive terminal connected to an output terminal.

## Claims

### Claim 1

A scanning line drive circuit having a configuration in which a plurality of unit circuits are connected in multiple stages,
wherein each of the unit circuits includes
a first transistor having a first conductive terminal to which a first-level voltage is applied and a second conductive terminal connected to a first node,
a second transistor having a second conductive terminal to which a second-level voltage is applied,
a third transistor having a first conductive terminal connected to the first node and a second conductive terminal connected to a first conductive terminal of the second transistor,
a fourth transistor having a first conductive terminal connected to a control terminal of the third transistor, and having a second conductive terminal and a control terminal to both of which the second-level voltage is applied, and
an output transistor having a control terminal connected to the first node and a second conductive terminal connected to an output terminal.

### Claim 2 (depends on 1)

The scanning line drive circuit according to claim 1, wherein the third transistor is a double gate transistor having two control terminals.

### Claim 3 (depends on 1)

The scanning line drive circuit according to claim 1, wherein the third transistor is a triple gate transistor having three control terminals.

### Claim 4 (depends on 1)

The scanning line drive circuit according to claim 1, wherein the third transistor is a multi-gate transistor having a plurality of control terminals.

### Claim 5 (depends on 1)

The scanning line drive circuit according to claim 1, wherein
the first to fourth transistors and the output transistor are p-channel transistors,
the first-level voltage is a high-level voltage, and
the second-level voltage is a low-level voltage.

### Claim 6 (depends on 1)

The scanning line drive circuit according to claim 1, wherein
an output signal of a unit circuit in a preceding stage is provided to a control terminal of the first transistor, and
a clock signal is provided to a control terminal of the second transistor, and
the first-level voltage is applied to a first conductive terminal of the output transistor.

### Claim 7 (depends on 1)

A display device comprising:
a plurality of pixel circuits each including a light-emitting element; and
the scanning line drive circuit according to claim 1.