# US 12,118,946 B2 · Scan circuit and display apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,118,946 B2 - Document ID: US12118946B2 - Status: Granted - Kind: B2 - Application number: 18/004,899 - Filed: 2022-02-16 - Published: 2024-07-25 - Granted: 2024-10-15 - Earliest claimed: 2022-02-16 - Assignees: Chengdu Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd.; BOE Technology Group Co., Ltd. - Inventors: Guanghua Xu; Yang Yu; Taofeng Xie - Web page: https://patentgrep.com/patent/US12118946B2 ## CPC - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - H10K 59/1213: {the pixel elements being TFTs} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements - G09G 2330/021: Power management, e.g. power saving - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract A scan circuit is provided, including first, second and third control signal driving circuits; wherein, in a first region, the first control signal driving circuit includes L stages, L being an integer ≥1; in a second region, the second control signal driving circuit includes M1 stages and the third control signal driving circuit includes M2 stages, M1, M2 each being an integer ≥1; in a third region, the first control signal driving circuit includes N1 stages, the second control signal driving circuit includes N2 stages, and the third control signal driving circuit includes N3 stages, N1, N2, N3 each being an integer ≥2; and the first region, the second region, and the third region surround a first portion, a second portion, and a third portion of a perimeter of a display region, respectively, the first portion, the second portion, and the third portion being at least partially non-overlapping. ## Claims ### Claim 1 A scan circuit, comprising a first control signal driving circuit, a second control signal driving circuit, and a third control signal driving circuit; wherein, in a first region, the first control signal driving circuit comprises L stages, L being an integer ≥1; in a second region, the second control signal driving circuit comprises M1 stages and the third control signal driving circuit comprises M2 stages, M1 being an integer ≥1, M2 being an integer ≥1; in a third region, the first control signal driving circuit comprises N1 stages, the second control signal driving circuit comprises N2 stages, and the third control signal driving circuit comprises N3 stages, N1 being an integer ≥2, N2 being an integer ≥2, N3 being an integer ≥2; and the first region, the second region, and the third region surround a first portion, a second portion, and a third portion of a perimeter of a display region, respectively, the first portion, the second portion, and the third portion being at least partially non-overlapping. ### Claim 2 (depends on 1) The scan circuit of claim 1, wherein the first portion, the second portion, and the third portion are completely non-overlapping. ### Claim 3 (depends on 1) The scan circuit of claim 1, wherein a stage of the M1 stages and a stage of the N2 stages are two consecutive stages of the second control signal driving circuit; a stage of the M2 stages and a stage of the N3 stages are two consecutive stages of the third control signal driving circuit; and a stage of L stages and a stage of N1 stages are two consecutive stages of the first control signal driving circuit. ### Claim 4 (depends on 1) The scan circuit of claim 1, wherein the N2 stages of the second control signal driving circuit, the N1 stages of the first control signal driving circuit, and the N3 stages of the third control signal driving circuit are arranged along a same direction; and the L stages of the first control signal driving circuit is displaced from the M1 stages of the second control signal driving circuit and the M2 stages of the third control signal driving circuit which are arranged along a same direction. ### Claim 5 (depends on 1) The scan circuit of claim 1, wherein the N2 stages of the second control signal driving circuit, the N1 stages of the first control signal driving circuit, and the N3 stages of the third control signal driving circuit are arranged in three rows in the third region, each row surrounding the third portion; the M1 stages of the second control signal driving circuit and the M2 stages of the third control signal driving circuit are arranged in two rows in the second region, each row surrounding the second portion; and the L stages of the first control signal driving circuit are arranged in one row surrounding the first portion. ### Claim 6 (depends on 5) The scan circuit of claim 5, further comprising one or more signal lines connecting the L stages of the first control signal driving circuits in the first region and the N1 stages of the first control signal driving circuits in the third region; and at least one of the one or more signal lines surrounds the second portion, and extends through the second region. ### Claim 7 (depends on 6) The scan circuit of claim 6, wherein at least one of the one or more signal lines is between a first row of the M1 stages of the second control signal driving circuit and a second row of the M2 stages of the third control signal driving circuit. ### Claim 8 (depends on 6) The scan circuit of claim 6, wherein the one or more signal lines comprise an input signal line of a first stage of the N1 stages of the first control signal driving circuit, extending through the second region and connected to an output terminal of a last stage of the L stages of the first control signal driving circuit. ### Claim 9 (depends on 6) The scan circuit of claim 6, wherein the one or more signal lines comprise at least one signal line having a first segment and a second segment coupled to each other; the first segment at least partially extends in the first region; the second segment at least partially extends in the second region; the first segment is in a second conductive layer; and the second segment is in a first signal line layer different from the second conductive layer. ### Claim 10 (depends on 9) The scan circuit of claim 9, wherein the first segment in the first region is adjacent to L number of output signal lines configured to transmit output signals from the L stages of the first control signal driving circuit in the first region, respectively; the first segment and segments of the L number of output signal lines in the first region are between the L stages of the first control signal driving circuit and the display region; and the L number of output signal lines is in a third conductive layer different from the first signal line layer and the second conductive layer. ### Claim 11 (depends on 1) The scan circuit of claim 1, further comprising L number of output signal lines connected to the L stages of the first control signal driving circuit in the first region, respectively; the L number of output signal lines extend from the first region into the second region by different length; and the L number of output signal lines are coupled to (j*L) number of rows of subpixels, respectively, j being an integer ≥1. ### Claim 12 (depends on 11) The scan circuit of claim 11, wherein, in the second region, the M1 stages of the second control signal driving circuit are on a side of the M2 stages of the third control signal driving circuit away from the display region; and segments of the L number of output signal lines in the second region are on a side of the M2 stages of the third control signal driving circuit closer to the display region. ### Claim 13 (depends on 1) The scan circuit of claim 1, wherein the M1 stages and P1 null stages of the second control signal driving circuit are arranged in a first row and (M1+P1) columns in the second region, the first row surrounding the second portion; and the M2 stages and P2 null stages of the third control signal driving circuit are arranged in a second row and (M2+P2) columns in the second region, the second row surrounding the second portion. ### Claim 14 (depends on 13) The scan circuit of claim 13, wherein a p1-th null stage and an m1-th stage of the second control signal driving circuit have a same circuit structure; the p1-th null stage is disconnected from subpixels in the display region; the m1-th stage is electrically connected to one or more subpixels in the display region; a p2-th null stage and an m2-th stage of the third control signal driving circuit have a same circuit structure; the p2-th null stage is disconnected from subpixels in the display region; and the m2-th stage is electrically connected to one or more subpixels in the display region. ### Claim 15 (depends on 1) The scan circuit of claim 1, wherein, in the third region, the N2 stages of the second control signal driving circuit, the N1 stages of the first control signal driving circuit, and the N3 stages of the third control signal driving circuit are sequentially arranged along the same direction from the third region toward the display region; and in the second region, the M1 stages of the second control signal driving circuit and the M2 stages of the third control signal driving circuit are sequentially arranged along a same direction from the second region toward the display region. ### Claim 16 (depends on 1) The scan circuit of claim 1, wherein, in the third region, the N1 stages of the first control signal driving circuit, the N2 stages of the second control signal driving circuit, and the N3 stages of the third control signal driving circuit are sequentially arranged along the same direction from the third region toward the display region; and in the second region, the M1 stages of the second control signal driving circuit and the M2 stages of the third control signal driving circuit are sequentially arranged along a same direction from the second region toward the display region. ### Claim 17 (depends on 1) The scan circuit of claim 1, wherein, in the third region, the N2 stages of the second control signal driving circuit, the N3 stages of the third control signal driving circuit, and the N1 stages of the first control signal driving circuit are sequentially arranged along the same direction from the third region toward the display region; and in the second region, the M1 stages of the second control signal driving circuit and the M2 stages of the third control signal driving circuit are sequentially arranged along a same direction from the second region toward the display region. ### Claim 18 (depends on 1) The scan circuit of claim 1, wherein the first control signal driving circuit, the second control signal driving circuit, and the third control signal driving circuit are three different control signal driving circuits selected from a first gate scanning signal driving circuit, a light emission control signal driving circuit, and a second gate scanning signal driving circuit. ### Claim 19 (depends on 1) A display apparatus, comprising the scan circuit of claim 1, and a display panel comprising a plurality of pixel driving circuits and a plurality of light emitting elements driven by the plurality of pixel driving circuits; wherein the scan circuit is configured to transmit control signals to the plurality of pixel driving circuits; the first control signal driving circuit is configured to transmit gate scanning signals to first N-type transistors in the plurality of pixel driving circuits and reset control signals to second N-type transistors in the plurality of pixel driving circuits; the second control signal driving circuit is configured to transmit light emission control signals to light emission control transistors in the plurality of pixel driving circuits; and the third control signal driving circuit is configured to transmit gate scanning signals to P-type transistors in the plurality of pixel driving circuits. ### Claim 20 (depends on 19) The display apparatus of claim 19, wherein at least the second region is at a corner of the display apparatus.