# US 12,118,936 B2 · Pixel circuit and driving method thereof and display panel having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,118,936 B2 - Document ID: US12118936B2 - Status: Granted - Kind: B2 - Application number: 18/119,635 - Filed: 2023-03-09 - Published: 2023-09-14 - Granted: 2024-10-15 - Earliest claimed: 2022-03-11 - Assignees: Electronics and Telecommunications Research Institute; Iucf-Hyu (Industry-University Cooperation Foundation Hanyang University) - Applicants: Electronics and Telecommunications Research Institute; IUCF-HYU (Industry-University Cooperation Foundation Hanyang University) - Inventors: Chun Won Byun; Chan Mo Kang; Nam Sung Cho; Byong Deok Choi; Yong Duck Kim - Web page: https://patentgrep.com/patent/US12118936B2 ## CPC - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/2007: {Display of intermediate tones} - G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)} - G09G 2300/0465: Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0202: Addressing of scan or signal lines - G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2330/028: Generation of voltages supplied to electrode drivers in a matrix display other than LCD - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A pixel circuit may comprise: a first transistor having a first terminal connected to a data line and to which a data signal is applied and a gate terminal connected to a scan line and to which a scan signal is applied; a third transistor having a gate terminal connected to a second terminal of the first transistor and a second terminal connected to a light emitting device; a capacitor having a second terminal commonly connected to the second terminal of the first transistor and the gate terminal of the third transistor; and a second transistor having a second terminal commonly connected to a first terminal of the capacitor and a first terminal of the third transistor, a first terminal connected to a first power supply voltage, and a gate terminal connected to an emission line to which an emission signal is applied. ## Claims ### Claim 1 A pixel circuit configured to supply a current to a light emitting device so that the light emitting device emits light of a desired grayscale, the pixel circuit comprising: a first transistor having a first terminal connected to a data line and to which a data signal is applied and a gate terminal connected to a scan line and to which a scan signal is applied; a third transistor having a gate terminal connected to a second terminal of the first transistor and a second terminal connected to the light emitting device; a capacitor having a second terminal commonly connected to the second terminal of the first transistor and the gate terminal of the third transistor; and a second transistor having a second terminal commonly connected to a first terminal of the capacitor and a first terminal of the third transistor, a first terminal connected to a first power supply voltage, and a gate terminal connected to an emission line to which an emission signal is applied, wherein, in a pre-charge period of a single operation cycle period, a gate voltage node of the third transistor is charged with an initial voltage, and a source voltage node of the third transistor is charged with the first power supply voltage, and wherein, in a data input period following a threshold voltage sampling period of the single operation cycle period, the first transistor maintains a turned-on state by the scan signal, the second transistor maintains a turned-off state by the emission signal, the data signal is applied to the gate terminal of the third transistor through the first transistor and the third transistor maintains a turned-off state and coupling occurs by parasitic capacitors seen at the gate voltage node and the source voltage node. ### Claim 2 (depends on 1) The pixel circuit of claim 1, wherein, in the pre-charge period of a single operation cycle period, the first transistor is turned on by the scan signal and the second transistor maintains a turned-on state by the emission signal. ### Claim 3 (depends on 2) The pixel circuit of claim 2, wherein, in the threshold voltage sampling period following the pre-charge period of the single operation cycle period, the first transistor maintains a turned-on state by the scan signal, the second transistor is turned off by the emission signal, and the source voltage node is discharged by a source follower until a voltage corresponding to a sum of absolute values of the initial voltage and the threshold voltage is reached or until the third transistor is turned off. ### Claim 4 (depends on 3) The pixel circuit of claim 3, wherein, in the data input period following the threshold voltage sampling period of the single operation cycle period, the source voltage node is charged with a source voltage reflecting the coupling by a data voltage supplied through the first transistor. ### Claim 5 (depends on 4) The pixel circuit of claim 4, wherein, in a display period following the data input period of the single operation cycle period, the first transistor is turned off by the scan signal, the second transistor is turned on by the emission signal, the coupling occurs by the parasitic capacitors seen at the gate voltage node and the source voltage node, and a gate voltage of the gate voltage node becomes a voltage reflecting two parasitic capacitor components at both ends of the capacitor by the first power supply voltage supplied through the second transistor. ### Claim 6 (depends on 5) The pixel circuit of claim 5, wherein a current flowing through the light emitting device according to the gate voltage has a coefficient having a sum of the capacitor and the parasitic capacitor as a denominator and the parasitic capacitor as a numerator in a threshold voltage component of the third transistor in an equation expressing the current. ### Claim 7 (depends on 1) The pixel circuit of claim 1, wherein the light emitting device includes at least one or more of an OLED, a micro-LED, and a QLED. ### Claim 8 A method of driving a pixel circuit configured to supply a current to a light emitting device so that the light emitting device emits light of a desired grayscale, the pixel circuit comprising: a first transistor having a first terminal connected to a data line and to which a data signal is applied and a gate terminal connected to a scan line and to which a scan signal is applied; a third transistor having a gate terminal connected to a second terminal of the first transistor and a second terminal connected to the light emitting device; a capacitor having a second terminal commonly connected to the second terminal of the first transistor and the gate terminal of the third transistor; and a second transistor having a second terminal commonly connected to a first terminal of the capacitor and a first terminal of the third transistor, a first terminal connected to a first power supply voltage, and a gate terminal connected to an emission line to which an emission signal is applied, the method comprising: charging a gate voltage node of the third transistor with an initial voltage, and charging a source voltage node of the third transistor with the first power supply voltage; in a state in which the second transistor is turned off, discharging a source voltage of the source voltage node by a source follower until a voltage corresponding to a sum of absolute values of the initial voltage and the threshold voltage is reached or until the third transistor is turned off; and in a state in which the third transistor is turned off, when coupling occurs by parasitic capacitors seen at the gate voltage node and the source voltage node, charging the source voltage node with a source voltage reflecting the coupling between the capacitor and the parasitic capacitor by a data voltage supplied through the first transistor. ### Claim 9 (depends on 8) The method of claim 8, further comprising: in a state in which the first transistor is turned off and the second transistor is turned on, when the coupling occurs by the parasitic capacitors seen at the gate voltage node and the source voltage node, causing a gate voltage of the gate voltage node to be a voltage reflecting the coupling by two parasitic capacitors of both ends of the capacitor by the first power supply voltage supplied through the second transistor. ### Claim 10 (depends on 8) The method of claim 8, wherein the light emitting device includes at least one or more of an OLED, a micro-LED, and a QLED. ### Claim 11 A display panel configured to output an image, the display panel comprising: a pixel unit in which a plurality of pixels are arranged; and a pixel circuit provided in a first pixel among the pixels, and configured to supply a current to a light emitting device so that the light emitting device belonging to the first pixel emits light of a desired grayscale, wherein the pixel circuit comprises: a first transistor having a first terminal connected to a data line and to which a data signal is applied and a gate terminal connected to a scan line and to which a scan signal is applied; a third transistor having a gate terminal connected to a second terminal of the first transistor and a second terminal connected to the light emitting device; a capacitor having a second terminal commonly connected to the second terminal of the first transistor and the gate terminal of the third transistor; and a second transistor having a second terminal commonly connected to a first terminal of the capacitor and a first terminal of the third transistor, a first terminal connected to a first power supply voltage, and a gate terminal connected to an emission line to which an emission signal is applied, wherein, in a pre-charge period of a single operation cycle period, a gate voltage node of the third transistor is charged with an initial voltage, and a source voltage node of the third transistor is charged with the first power supply voltage, and wherein, in a data input period following a threshold voltage sampling period of the single operation cycle period, the first transistor maintains a turned-on state by the scan signal, the second transistor maintains a turned-off state by the emission signal, the data signal is applied to the gate terminal of the third transistor through the first transistor and the third transistor maintains a turned-off state and coupling occurs by parasitic capacitors seen at the gate voltage node and the source voltage node. ### Claim 12 (depends on 11) The display panel of claim 11, further comprising: a data driver configured to supply the data signal to the pixel unit; a gate driver configured to supply the scan signal to the pixel unit; and a timing controller configured to control operations of the data driver and the gate driver. ### Claim 13 (depends on 12) The display panel of claim 12, wherein the data driver applies, as the data signal, a pulse amplitude modulation (PAM) signal having a plurality of levels to the first terminal of the first transistor according to a grayscale required for the light emitting device coupled to each pixel. ### Claim 14 (depends on 13) The display panel of claim 13, wherein the gate driver applies, as the scan signal, a pulse width modulation (PWM) signal having a plurality of sub-frames in a single frame according to the grayscale to a control terminal of the first transistor, and a PAM signal of any one level selected from the PAM signal is applied to the gate terminal of the third transistor configured to supply a grayscale current to the light emitting device during a corresponding sub-frame. ### Claim 15 (depends on 13) The display panel of claim 13, wherein the number of output channels of a decoder provided in the data driver is smaller than the number of grayscales that is expressed with predetermined bits. ### Claim 16 (depends on 11) The display panel of claim 11, wherein, in the pre-charge period of a single operation cycle period of the first pixel, the first transistor is turned on by the scan signal and the second transistor maintains a turned-on state by the emission signal. ### Claim 17 (depends on 16) The display panel of claim 16, wherein, in the threshold voltage sampling period following the pre-charge period of the single operation cycle period, the first transistor maintains a turned-on state by the scan signal, the second transistor is turned off by the emission signal, and the source voltage node is discharged by a source follower until a voltage corresponding to a sum of absolute values of the initial voltage and the threshold voltage is reached or until the third transistor is turned off. ### Claim 18 (depends on 17) The display panel of claim 17, wherein, in the data input period following the threshold voltage sampling period of the single operation cycle period, the source voltage node is charged with a source voltage reflecting the coupling with the parasitic capacitor by a data voltage supplied through the first transistor. ### Claim 19 (depends on 18) The display panel of claim 18, wherein, in a display period following the data input period of the single operation cycle period, the first transistor is turned off by the scan signal, the second transistor is turned on by the emission signal, the coupling occurs by the parasitic capacitors seen at the gate voltage node and the source voltage node, and a gate voltage of the gate voltage node becomes a voltage reflecting the coupling at both ends of the capacitor by the first power supply voltage supplied through the second transistor. ### Claim 20 (depends on 11) The display panel of claim 11, wherein the light emitting device includes at least one or more of an OLED, a micro-LED, and a QLED.