# US 12,118,929 B2 · Light emitting display device and driving method of the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,118,929 B2 - Document ID: US12118929B2 - Status: Granted - Kind: B2 - Application number: 17/746,129 - Filed: 2022-05-17 - Published: 2022-12-01 - Granted: 2024-10-15 - Earliest claimed: 2021-05-27 - Assignees: LG Display Co., Ltd. - Applicants: LG Display Co., Ltd. - Inventors: Sung Chul Ha; Jin Cheol Hong - Web page: https://patentgrep.com/patent/US12118929B2 ## CPC - G09G 3/3208: organic, e.g. using organic light-emitting diodes [OLED] - G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements - G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)} - G09G 2300/0814: used for selection purposes, e.g. logical AND for partial update - G09G 2300/0857: Static memory circuit, e.g. flip-flop - G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/0294: Details of sampling or holding circuits arranged for use in a driver for data electrodes - G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes - G09G 2330/06: Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation - G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit - G09G 2370/10: Use of a protocol of communication by packets in interfaces along the display data pipeline - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display device includes a display panel configured to display an image, a data driver configured to supply a data voltage to the display panel, and a timing controller configured to control the data driver, and the data driver pauses a data latch operation. ## Claims ### Claim 1 A light emitting display device comprising: a display panel configured to display an image; a data driver configured to supply a data voltage to the display panel; and a timing controller configured to identify an amplifier activation event and provide a data signal to control data latch operation of the data driver based on the amplifier activation event, wherein the data driver is configured to pause the data latch operation during conversion of the data signal into the data voltage during a power noise event caused by the amplifier activation event within the data driver. ### Claim 2 (depends on 1) The light emitting display device according to claim 1, wherein the data driver pauses the data latch operation based on a falling time or a rising time of a source output enable signal. ### Claim 3 (depends on 1) The light emitting display device according to claim 1, wherein the pause of the data latch operation is based on a latch hold signal generated from the data driver or the timing controller. ### Claim 4 (depends on 3) The light emitting display device according to claim 3, wherein the data driver comprises a shift register configured to pause output of a clock signal based on the latch hold signal. ### Claim 5 (depends on 4) The light emitting display device according to claim 4, wherein the shift register comprises: an AND gate configured to AND the latch hold signal and a shift clock signal and to output a resultant signal; and a flip-flop configured to output the clock signal based on the signal output from the AND gate and a pulse externally applied thereto. ### Claim 6 (depends on 5) The light emitting display device according to claim 5, wherein, when the latch hold signal is generated with a logic low level, a latch connected to the shift register has a latch hold period in which the latch pauses the data latch operation. ### Claim 7 (depends on 4) The light emitting display device according to claim 4, wherein the shift register comprises: an inverter configured to invert the latch hold signal and to output an inverted latch hold signal; an AND gate configured to AND the inverted latch hold signal output from the inverter and a shift clock signal and to output a resultant signal; and a flip-flop configured to output the clock signal based on the signal output from the AND gate and a pulse externally applied thereto. ### Claim 8 (depends on 7) The light emitting display device according to claim 7, wherein, when the latch hold signal is generated with a logic high level, a latch connected to the shift register has a latch hold period in which the latch pauses the data latch operation. ### Claim 9 (depends on 1) The light emitting display device according to claim 1, wherein the data driver is configured generate a latch hold signal based on a noise generation event or an output event of the data driver. ### Claim 10 (depends on 1) The light emitting display device according to claim 1, wherein the data driver is configured to pause the data latch operation based on an embedded clock point-to-point interface (EPI) signal from the timing controller, wherein the timing controller generates a latch hold signal based on a noise generation event or an output event of the data driver. ### Claim 11 (depends on 1) The light emitting display device according to claim 1, wherein the pause occurs after latching first data for a first channel and before latching data for a second channel, wherein the second channel is adjacent to the first channel. ### Claim 12 A method for driving a light emitting display device including a display panel configured to display an image, a data driver configured to supply a data voltage to the display panel, and a timing controller configured to control the data driver, comprising: identify activation event; transferring, to the data driver, data comprising a control packet and a data packet via an interface coupled between the timing controller and the data driver; and during conversion of the data packet into the data voltage, delaying a data latch operation during a latch hold period based on noise caused by the amplifier activation event in the data driver. ### Claim 13 (depends on 12) The method according to claim 12, wherein, the latch hold period is generated based on a falling time or a rising time of a source output enable signal activating output of the data driver. ### Claim 14 (depends on 12) The method according to claim 12, wherein the data latch operation comprises selecting an output channel for a portion of the data packet, wherein the portion of the data packet is converted into a voltage for driving the light emitting display device. ### Claim 15 A data driver, comprising: a shift register configured to receive a data signal from a timing controller and output a clock signal; a latch configured to latch the data signal based on the clock signal; a digital to analog converter (DAC) configured to convert the data signal into data voltages to drive a display device; and an output amplifier circuit configured to output the data voltages, wherein the data driver is further configured to interrupt and delay latching of the data signal based on a latch hold signal associated with noise caused by an activation event of the output amplifier circuit. ### Claim 16 (depends on 15) The data driver of claim 15, wherein the shift register is configured to delay the clock signal to interrupt and delay latching of the data signal. ### Claim 17 (depends on 15) The data driver of claim 15, wherein the interrupt and delay occurs after latching first data for a first channel and before latching data for a second channel, wherein the second channel is adjacent to the first channel. ### Claim 18 (depends on 15) The data driver of claim 15, wherein the latch hold signal is included in an embedded clock point-to-point interface (EPI) signal from the timing controller.