# US 12,118,925 B2 · Driving signals and driving circuits in display device and driving method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,118,925 B2 - Document ID: US12118925B2 - Status: Granted - Kind: B2 - Application number: 18/243,406 - Filed: 2023-09-07 - Published: 2023-12-28 - Granted: 2024-10-15 - Earliest claimed: 2020-10-12 - Assignees: Au Optronics Corporation - Applicants: AU Optronics Corporation - Inventors: Che-Chia Chang; Shang-Jie Wu; Yu-Chieh Kuo; Hsien-Chun Wang; Sin-An Lin; Mei-Yi Li; Yu-Hsun Chiu; Ming-Hung Chuang; Yi-Jung Chen - Web page: https://patentgrep.com/patent/US12118925B2 ## CPC - G09G 3/2014: {by modulation of the duration of a single pulse during which the logic level remains constant} - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G09G 3/14: Semiconductor devices, e.g. diodes - G09G 3/2007: {Display of intermediate tones} - G09G 2300/0809: Several active elements per pixel in active matrix panels - G09G 2300/0828: forming a digital to analog [D/A] conversion circuit - G09G 2300/0866: by means of changes in the pixel supply voltage - G09G 2310/0259: with use of an analog or digital ramp generator in the column driver or in the pixel circuit - G09G 2310/061: for resetting or blanking - G09G 2310/067: Special waveforms for scanning, where no circuit details of the gate driver are given - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G 2330/12: Test circuits or failure detection circuits included in a display system, as permanent part thereof - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current flowing through one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current. ## Claims ### Claim 1 A display device, comprising: a plurality of light emitting elements; and a plurality of driving circuits, each of the driving circuits is configured to generate a driving current to drive one of the light emitting elements to emit light, wherein each of the driving circuits comprises: a first transistor, wherein the first transistor is a P type-transistor; a second transistor, wherein the second transistor is an N-type transistor, wherein the second transistor is configured to control timing of a rising edge of the driving current in an emission period, wherein the second transistor is directly connected to the one of the light emitting elements, and wherein the driving current flows from a first system high voltage terminal sequentially through the first transistor, the second transistor and the one of the light emitting elements to a system low voltage terminal; a reset circuit, configured to reset a voltage level of a gate terminal of the second transistor; a first control circuit, configured to control the first transistor to adjust pulse amplitude of the driving current; and a second control circuit, configured to control the second transistor to adjust a pulse width of the driving current, and configured to control the second transistor, according to a corresponding one of a plurality of sweep signals, to adjust a phase of the driving current, wherein each of the driving circuits provides the driving current at different time points according to the sweep signals. ### Claim 2 (depends on 1) The display device of claim 1, wherein the display device simultaneously provides a plurality of first data signals to the driving circuits during a global scanning period, and wherein the display device sequentially provides the sweep signals to the driving circuits during a progressive scanning period. ### Claim 3 (depends on 1) The display device of claim 1, wherein the reset circuit comprising: a third transistor, with a first terminal electrically coupled to the gate terminal of the second transistor, with a gate configured to receive a first control signal; and a first capacitor, with a first terminal electrically coupled to the gate terminal of the second transistor and the first terminal of the third transistor, with a second terminal electrically coupled to a second terminal of the third transistor. ### Claim 4 (depends on 1) The display device of claim 1, wherein the first control circuit comprising: a second capacitor, with a first terminal electrically coupled to the first system high voltage terminal, with a second terminal electrically coupled to a gate terminal of the first transistor; and a fourth transistor, with a first terminal configured to receive one of a plurality of first data signals, with a second terminal electrically coupled to a gate terminal of the first terminal and the second terminal of the second capacitor, with a gate terminal configured to receive a second control signal. ### Claim 5 (depends on 1) The display device of claim 1, wherein the first control circuit comprising: a second capacitor, with a first terminal electrically coupled to the first system high voltage terminal, with a second terminal electrically coupled to a gate terminal of the first transistor; a fourth transistor, with a first terminal configured to receive one of a plurality of first data signals, with a second terminal electrically coupled to a first terminal of the first transistor, with a gate terminal configured to receive a second control signal; a fifth transistor, with a first terminal electrically coupled to a gate terminal of the first transistor, with a second terminal electrically coupled to a second terminal of the first transistor, with a gate terminal configured to receive the second control signal; and a sixth transistor, with a first terminal electrically coupled to the first terminal of the fifth transistor, with a second terminal configured to receive a third control signal, with a gate terminal configured to receive the third control signal. ### Claim 6 (depends on 1) The display device of claim 1, wherein the second control circuit comprising: a seventh transistor, with a first terminal configured to receive one of a plurality of second data signals, with a gate terminal configured to receive a fourth control signal; an eighth transistor, with a first terminal electrically coupled to a second system high voltage terminal, with a gate terminal electrically coupled to a second terminal of the seventh transistor; a ninth transistor, with a first terminal electrically coupled to a second terminal of the eighth transistor, with a second terminal electrically coupled to the gate terminal of the second transistor, with a gate terminal configured to receive a fifth control signal; and a third capacitor, with a first terminal configured to receive the corresponding one of the sweep signals, with a second terminal electrically coupled to the gate terminal of the eighth transistor. ### Claim 7 (depends on 1) The display device of claim 1, wherein the second control circuit comprising: a seventh transistor, with a first terminal configured to receive one of a plurality of second data signals, with a gate terminal configured to receive a fourth control signal; an eighth transistor, with a first terminal electrically coupled to a second terminal of the seventh transistor; a ninth transistor, with a first terminal electrically coupled to a second terminal of the eighth transistor, with a second terminal electrically coupled to the gate terminal of the second transistor, with a gate terminal configured to receive a fifth control signal; a tenth transistor, with a first terminal electrically coupled to a second system high voltage terminal, with a second terminal electrically coupled to the second terminal of the seventh transistor and the first terminal of the eighth transistor, with a gate terminal configured to receive the fifth control signal; a third capacitor, with a first terminal configured to receive the corresponding one of the sweep signals, with a second terminal electrically coupled to a gate terminal of the eighth transistor; an eleventh transistor, with a first terminal electrically coupled to the second terminal of the third capacitor and the gate terminal of the eighth transistor, with a second terminal electrically coupled to the second terminal of the eighth transistor and the first terminal of the ninth transistor, with a gate terminal configured to receive the fourth control signal; and a twelfth transistor, with a first terminal electrically coupled to the second terminal of the third capacitor, the gate terminal of the eighth transistor and the first terminal of the eleventh transistor, with a second terminal configured to receive a sixth control signal, with a gate terminal configured to receive the sixth control signal. ### Claim 8 (depends on 1) The display device of claim 1, further comprising: a thirteenth transistor, with a first terminal electrically coupled to the first system high voltage terminal, with a second terminal electrically coupled to a first terminal of the first transistor, with a gate terminal configured to receive a fifth control signal, wherein a second terminal of the first transistor is electrically coupled to a first terminal of the second transistor, wherein a first terminal of the one of the light emitting elements is electrically coupled to a second terminal of the second transistor, and wherein a second terminal of the one of the light emitting elements is electrically coupled to the system low voltage terminal. ### Claim 9 A display device, comprising: a plurality of light emitting element; and a plurality of driving circuit, each of the driving circuits is configured to generate a driving current to drive one of the light emitting elements to emit light, wherein each of the driving circuits comprises: a first transistor, wherein the first transistor is a P type transistor; a second transistor, wherein the first transistor is an N type transistor, wherein the second transistor is configured to control timing of a rising edge of the driving current in an emission period, wherein the second transistor is directly connected to the one of the light emitting elements, and wherein the first transistor, the second transistor and the one of the light emitting elements are sequentially connected in series between a first system high voltage terminal to a system low voltage terminal; a reset circuit, electrically coupled to a gate terminal of the second transistor; a first control circuit, electrically coupled to a gate terminal of the first transistor, and configured to control the first transistor to adjust pulse amplitude of the driving current; and a second control circuit, electrically coupled to the gate terminal of the second transistor, and configured to control the second transistor to adjust a pulse width of the driving current, and configured to control the second transistor, according to a corresponding one of a plurality of sweep signals, to adjust a phase of the driving current, wherein each of the driving circuits provides the driving current at different time points according to the sweep signals. ### Claim 10 A driving method, for driving a display device with a plurality of driving circuits and a plurality of light emitting elements, wherein each of the driving circuits is configured to generate a driving current to drive the one of the light emitting elements to emit light, wherein each of the driving circuits comprises a first transistor configured to control pulse amplitude of the driving current and a second transistor configured to control pulse width of the driving current, wherein the first transistor, the second transistor and the one of the light emitting elements are sequentially connected in series between a first system high voltage terminal to a system low voltage terminal, wherein the first transistor is a P-type transistor, wherein the second transistor is an N-type transistor, wherein the second transistor is configured to control timing of a rising edge of the driving current in an emission period, wherein the second transistor is directly connected to the one of the light emitting elements, and wherein the driving method comprising: during a global scanning period, simultaneously providing a plurality of first data signals to the driving circuits according to color of each of the light emitting elements to be display; and during a progressive scanning period, sequentially providing a plurality of second data signals to the driving circuits according to gray level of each of the light emitting elements to be display, and sequentially providing a plurality of sweep signals to the driving circuits, wherein each of the driving circuits generates the driving current, according to the one of the first data signals, to drive the one of the light emitting elements to emit light, and wherein each of the driving circuits starts generating the driving current according to one of the second data signals.