# US 12,118,923 B2 · Driving circuit for display panel

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- Number: US 12,118,923 B2
- Document ID: US12118923B2
- Status: Granted
- Kind: B2
- Application number: 18/091,788
- Filed: 2022-12-30
- Published: 2023-12-14
- Granted: 2024-10-15
- Earliest claimed: 2021-12-30
- Assignees: Sitronix Technology Corp.
- Applicants: Sitronix Technology Corp.
- Inventors: Chung-Hsin Su
- Web page: https://patentgrep.com/patent/US12118923B2

## CPC

- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0452: Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/06: Details of flat display driving waveforms
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0204: Compensation of DC component across the pixels in flat panels
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2330/06: Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present application provides a driving circuit for display panel, which comprises a driving-signal generating circuit generating a driving signal in a frame time for driving a display element of a display panel. The driving signal includes at least one first turn-on pulse width, at least one first turn-off pulse width, at least one second turn-on pulse width, and at least one second turn-off pulse width. The first turn-on pulse width is greater than the second turn-on pulse width. The first turn-off pulse width is smaller than the second turn-off pulse width. By adopting the driving circuit according to the present application, EMI may be reduced and the displaying quality may be improved.

## Claims

### Claim 1

A driving circuit for a display panel, comprising:
a driving-signal generating circuit, generating a driving signal in a frame time to drive a display element of said display panel, said driving signal including at least one first turn-on pulse width, at least one second turn-on pulse width, and at least one third turn-on pulse width, said first turn-on pulse width greater than said second turn-on pulse width and said third turn-on pulse width, said second turn-on pulse width smaller than said third turn-on pulse width;
wherein said driving-signal generating circuit generates said driving signal according to a clock signal with a plurality of clock pulses; the frequency of said clock signal is a first frequency, a second frequency, or a third frequency; said driving-signal generating circuit generates said first turn-on pulse width according to said clock signal with said first frequency, said second turn-on pulse width according to said clock signal with said second frequency, and said third turn-on pulse width according to said clock signal with said third frequency.

### Claim 2 (depends on 1)

The driving circuit of claim 1, wherein in a duration within said frame time, said driving-signal generating circuit first generates said second turn-on pulse width, then said first turn-on pulse width, and then said third turn-on pulse width.

### Claim 3 (depends on 1)

The driving circuit of claim 1, wherein in a duration within said frame time, said driving-signal generating circuit first generates said second turn-on pulse width, then said third turn-on pulse width, and then said first turn-on pulse width.

### Claim 4 (depends on 1)

The driving circuit of claim 1, wherein said driving-signal generating circuit generates said first turn-on pulse width, said second turn-on pulse width, and said third turn-on pulse width according to a fixed number of clock pulses.

### Claim 5 (depends on 1)

The driving circuit of claim 1, wherein in a duration within said frame time, said driving-signal generating circuit first generates said second turn-on pulse width before generating said first turn-on pulse width or said third turn-on pulse width.

### Claim 6 (depends on 5)

The driving circuit of claim 5, wherein said at least one first turn-on pulse width includes a plurality of first turn-on pulse widths; said at least one second turn-on pulse width includes a plurality of second turn-on pulse widths; said at least one third turn-on pulse width includes a plurality of third turn-on pulse widths; beyond said duration within said frame time, said driving-signal generating circuit generates N first turn-on pulse widths of said plurality of first turn-on pulse widths, P second turn-on pulse widths of said plurality of second turn-on pulse widths, and Q third turn-on pulse widths of said plurality of third turn-on pulse widths sequentially; and N, P, Q are positive integers.

### Claim 7 (depends on 5)

The driving circuit of claim 5, wherein said at least one first turn-on pulse width includes a plurality of first turn-on pulse widths; said at least one second turn-on pulse width includes a plurality of second turn-on pulse widths; said at least one third turn-on pulse width includes a plurality of third turn-on pulse widths; beyond said duration within said frame time, said driving-signal generating circuit generates Q third turn-on pulse widths of said plurality of third turn-on pulse widths, P second turn-on pulse widths of said plurality of second turn-on pulse widths, and N first turn-on pulse widths of said plurality of first turn-on pulse widths sequentially; and N, P, Q are positive integers.

### Claim 8 (depends on 1)

The driving circuit of claim 1, wherein said frame time is the Fth frame time; said driving-signal generating circuit generates said driving signal in the (F−1) th frame time and the (F+1) th frame time; said driving signal includes at least one of said first turn-on pulse width, said second turn-on pulse width, and third turn-on pulse width; the durations of said (F−1) th frame time, said Fth frame time, and said (F+1) th frame time are identical; and F is an integer greater than 2.

### Claim 9

A driving circuit for a display panel, comprising:
a driving-signal generating circuit, generating a driving signal in a frame time for driving a display element of said display pane, said driving signal including at least one first turn-on pulse width, at least one first turn-off pulse width, at least one second turn-on pulse width, and at least one second turn-off pulse width, said first turn-on pulse width greater than said second turn-on pulse width, and said first turn-off pulse width smaller than said second turn-off pulse width.

### Claim 10 (depends on 9)

The driving circuit of claim 9, wherein said first turn-on pulse width is equal to said second turn-off pulse width; and said second turn-on pulse width is equal to said first turn-off pulse width.

### Claim 11 (depends on 9)

The driving circuit of claim 9, wherein said driving-signal generating circuit generates said first turn-on pulse width and said second turn-on pulse width according to a fixed number of clock pulses.

### Claim 12 (depends on 11)

The driving circuit of claim 11, wherein said driving-signal generating circuit generates said driving signal according to a clock signal with a said clock pulses; the frequency of said clock signal changes from a first frequency to a second frequency gradually, and then from said second frequency to said first frequency gradually; said second frequency is greater than said first frequency; in the duration when the frequency of said clock signal changes from said first frequency to said second frequency, said driving-signal generating circuit generates said first turn-on pulse width and said first turn-off pulse width according to said clock signal; in the duration when the frequency of said clock signal changes from said second frequency to said first frequency, said driving-signal generating circuit generates said second turn-on pulse width and said second turn-off pulse width according to said clock signal.

### Claim 13

A driving circuit for a display panel, comprising:
a driving-signal generating circuit, generating a driving signal including a plurality of first turn-on pulse widths in the (F−1) th frame time for driving a display element of said display panel and a driving signal including a plurality of second turn-on pulse widths in the Fth frame time for driving said display element;
wherein said second turn-on pulse widths are different from said first turn-on pulse widths; the duration of the (F−1) th frame time is identical to the duration of the Fth frame time; and F is an integer greater than 2.

### Claim 14 (depends on 13)

The driving circuit of claim 13, wherein said driving-signal generating circuit generates said driving signal including a plurality of third turn-on pulse widths in the (F+1) th frame time for driving said display element; said third turn-on pulse widths are different from said first turn-on pulse widths and said second turn-on pulse widths; the duration of the (F−1) th frame time, the duration of the Fth frame time, and the duration of the (F+1) th frame time are identical.

### Claim 15 (depends on 14)

The driving circuit of claim 14, wherein said driving-signal generating circuit generates said first turn-on pulse widths, said second turn-on pulse widths, and said third turn-on pulse widths according to a fixed number of clock pulses.

### Claim 16 (depends on 15)

The driving circuit of claim 15, wherein said driving-signal generating circuit generates said driving signal according to a clock signal with said clock pulses; the frequency of said clock signal is a first frequency, a second frequency, or a third frequency; said driving-signal generating circuit generates said first turn-on pulse widths according to said clock signal with said first frequency, said second turn-on pulse widths according to said clock signal with said second frequency, and said third turn-on pulse widths according to said clock signal with said third frequency.