# US 12,118,911 B2 · Demultiplexer circuit, display panel and driving method of display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,118,911 B2 - Document ID: US12118911B2 - Status: Granted - Kind: B2 - Application number: 17/298,636 - Filed: 2021-05-10 - Published: 2024-01-11 - Granted: 2024-10-15 - Earliest claimed: 2021-04-26 - Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd. - Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd. - Inventors: Lifang Wang - Web page: https://patentgrep.com/patent/US12118911B2 ## CPC - G09G 3/2003: {Display of colours (specific for liquid crystal displays G09G3/3607)} - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns - G09G 2330/021: Power management, e.g. power saving - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Embodiments of the present application provide a demultiplexer circuit, a display panel and a driving method of a display panel. The display panel includes a first operating frequency and a second operating frequency. Responsive to the display panel being at the first operating frequency, the first switch unit is in a switched-on state and the second switch unit is in a switched-off state; responsive to the display panel being at the second operating frequency, both the first switch unit and the second switch unit are in the switched-on state. ## Claims ### Claim 1 A demultiplexer circuit, wherein the demultiplexer circuit comprises at least one demultiplexing module, and the demultiplexing module at least comprises a first switch unit and a second switch unit; a signal input end of the first switch unit and a signal input end of the second switch unit are connected to each other to form a data signal input end of the demultiplexing module, and a signal output end of the first switch unit and a signal output end of the second switch unit are connected to each other to form a data signal output end of the demultiplexing module; wherein the demultiplexing module further comprises a plurality of control signal lines, the control signal lines at least comprise a first control signal line and a second control signal line, a control end of the first switch unit is connected to the first control signal line, and a control end of the second switch unit is connected to the second control signal line; wherein the first control signal line outputs a first switch control signal to the first switch unit, and the second control signal line outputs a second switch control signal to the second switch unit; and wherein the first control signal line is electrically connected to an integrated circuit, the second control signal line is electrically connected to the first control signal line via a frequency-based switch, and a control end of the frequency-based switch is electrically connected to the integrated circuit. ### Claim 2 (depends on 1) The demultiplexer circuit according to claim 1, wherein the first control signal line and the second control signal line are electrically connected to an integrated circuit. ### Claim 3 (depends on 1) The demultiplexer circuit according to claim 1, wherein the first control signal line outputs a second switch control signal to the first switch unit, and the second control signal line outputs the second switch control signal to the second switch unit. ### Claim 4 (depends on 1) The demultiplexer circuit according to claim 1, wherein the first switch unit at least comprises a first switching transistor, and the second switch unit at least comprises a second switching transistor; wherein in the demultiplexing module, the first control signal line is electrically connected to a gate of the first switching transistor and the second control signal line is electrically connected to a gate of the second switching transistor. ### Claim 5 (depends on 4) The demultiplexer circuit according to claim 4, wherein a source of the first switching transistor and a source of the second switching transistor are connected to each other to form the data signal input end of the demultiplexing module; a drain of the first switching transistor and a drain of the second switching transistor are connected to each other to form the data signal output end of the demultiplexing module. ### Claim 6 (depends on 1) The demultiplexer circuit according to claim 1, wherein at least one of the first switch unit and the second switch unit comprises N switching transistors, where N is a positive integer greater than or equal to 2. ### Claim 7 (depends on 6) The demultiplexer circuit according to claim 6, wherein the first switch unit at least comprises a first switching transistor, and the second switch unit comprises a second switching transistor and a third switching transistor; wherein in the demultiplexing module, a gate of the first switch transistor is electrically connected to the first control signal line and a gate of the second switching transistor and a gate of the third switching transistor are electrically connected to the second control signal line. ### Claim 8 (depends on 7) The demultiplexer circuit according to claim 7, wherein a source of the first switching transistor, a source of the second switching transistor and a source of the third switching transistor are connected together to form the data signal input end of the demultiplexing module; a drain of the first switching transistor, a drain of the second switching transistor and a drain of the third switching transistor are connected together to form the data signal output end of the demultiplexing module. ### Claim 9 A display panel, comprising: a plurality of pixel units, any of the pixel units comprising a plurality of subpixels; a plurality of fanout lines, providing data signals for the pixel units; a demultiplexer circuit, comprising at least one demultiplexing module, the demultiplexing module at least comprising a first switch unit and a second switch unit; an integrated circuit, electrically connected to the demultiplexer circuit and providing control signals for the first switch unit and the second switch unit of the demultiplexer circuit; wherein any of the pixel units corresponds to a plurality of said demultiplexing modules; in the demultiplexing module, a signal input end of the first switch unit and a signal input end of the second switch unit are connected to each other to form a data signal input end of the demultiplexing module, and a signal output end of the first switch unit and a signal output end of the second switch unit are connected to each other to form a data signal output end of the demultiplexing module, and wherein the first control signal line is electrically connected to the integrated circuit, the second control signal line is electrically connected to the first control signal line via a frequency-based switch, and a control end of the frequency-based switch is electrically connected to the integrated circuit. ### Claim 10 (depends on 9) The display panel according to claim 9, wherein the data signal input ends of the demultiplexing modules of the demultiplexer circuit corresponding to a same pixel unit are fed with a same data signal by a same fanout line, and the data signal output end of any of the demultiplexing modules of the demultiplexer circuit is electrically connected to the subpixel. ### Claim 11 (depends on 9) The display panel according to claim 9, wherein the demultiplexing module further comprises a plurality of control signal lines, the control signal lines at least comprise a first control signal line and a second control signal line, a control end of the first switch unit is connected to the first control signal line, and a control end of the second switch unit is connected to the second control signal line. ### Claim 12 (depends on 11) The display panel according to claim 11, wherein the control ends of the first switch units of the demultiplexing modules corresponding to a same row of subpixels with a same color are connected to the same first control signal line, and the control ends of the second switch units of the demultiplexing modules corresponding to a same row of subpixels with a same color are connected to the same second control signal line. ### Claim 13 (depends on 11) The display panel according to claim 11, wherein the first control signal line outputs a first switch control signal to the first switch unit, and the second control signal line outputs a second switch control signal to the second switch unit. ### Claim 14 (depends on 13) The display panel according to claim 13, wherein the first control signal line and the second control signal line are electrically connected to the integrated circuit. ### Claim 15 (depends on 11) The display panel according to claim 11, wherein the first control signal line outputs a second switch control signal to the first switch unit, and the second control signal line outputs the second switch control signal to the second switch unit. ### Claim 16 A driving method of a display panel, the display panel comprising: a plurality of pixel units, any of the pixel units comprising a plurality of subpixels; a plurality of fanout lines, providing data signals for the pixel units; a demultiplexer circuit, comprising at least one demultiplexing module, the demultiplexing module at least comprising a first switch unit and a second switch unit; an integrated circuit, electrically connected to the demultiplexer circuit and providing control signals for the first switch unit and the second switch unit of the demultiplexer circuit; wherein any of the pixel units corresponds to a plurality of said demultiplexing modules; in the demultiplexing module, a signal input end of the first switch unit and a signal input end of the second switch unit are connected to each other to form a data signal input end of the demultiplexing module, and a signal output end of the first switch unit and a signal output end of the second switch unit are connected to each other to form a data signal output end of the demultiplexing module; the display panel further comprising a first operating frequency and a second operating frequency, wherein the first operating frequency is less than the second operating frequency; responsive to the display panel being at the first operating frequency, the first switch unit is in a switched-on state and the second switch unit is in a switched-off state; responsive to the display panel being at the second operating frequency, both the first switch unit and the second switch unit are in the switched-on state, and wherein the first control signal line is electrically connected to the integrated circuit, the second control signal line is electrically connected to the first control signal line via a frequency-based switch, and a control end of the frequency-based switch is electrically connected to the integrated circuit. ### Claim 17 (depends on 16) The driving method of the display panel according to claim 16, wherein the first operating frequency is for a low-frequency operating state and the second operating frequency is for a high-frequency operating state.