# US 12,118,910 B2 · Display panel and display device

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- Number: US 12,118,910 B2
- Document ID: US12118910B2
- Status: Granted
- Kind: B2
- Application number: 18/225,000
- Filed: 2023-07-21
- Published: 2023-11-09
- Granted: 2024-10-15
- Earliest claimed: 2021-08-06
- Assignees: Xiamen Tianma Micro-Electronics Co., Ltd.
- Applicants: Xiamen Tianma Micro-Electronics Co.,Ltd.
- Inventors: Yuheng Zhang
- Web page: https://patentgrep.com/patent/US12118910B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G 2310/0272: Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
- G09G 2310/061: for resetting or blanking
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
- G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, a data writing module, and a bias adjustment module. The driving module includes a driving transistor. The data writing module is configured to provide a data signal for the driving transistor. The bias adjustment module is configured to provide a bias adjustment signal for the driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage. The non-light-emitting stage includes a bias adjustment stage. At least one of a source or a drain of the driving transistor is configured to receive the bias adjustment signal in the bias adjustment stage. An operating state of the pixel circuit includes a first mode and a second mode.

## Claims

### Claim 1

A display panel comprising:
a pixel circuit including a driving module, a data writing module, and a bias adjustment module, the driving module including a driving transistor, the data writing module being configured to provide a data signal for the driving transistor, and the bias adjustment module being configured to provide a bias adjustment signal for the driving transistor; and
a light-emitting element;
wherein:
a time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, the non-light-emitting stage including a bias adjustment stage, at least one of a source or a drain of the driving transistor being configured to receive the bias adjustment signal in the bias adjustment stage;
an operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2;
L1>L2;
a working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame;
a time length of the bias adjustment stage in the first frame is W1, and a time length of the bias adjustment stage in the second frame is W2;
W2/W1≥1, and/or W2/W1<L1/L2.

### Claim 2 (depends on 1)

The display panel of claim 1, wherein:
the bias adjustment stage in the first frame includes N1 sub-bias adjustment stages, wherein N1≥1;
the bias adjustment stage in the second frame includes N2 sub-bias adjustment stages, wherein N2≥1; and
a time length of at least one sub-bias adjustment stage in the first frame is equal to a time length of at least one sub-bias adjustment stage in the second frame.

### Claim 3 (depends on 2)

The display panel of claim 2, wherein:
a time length of an ith sub-bias adjustment stage in the first frame is equal to a time length of an ith sub-bias adjustment stage in the second frame, wherein 1≤i≤N0; and
when N1≠N2, N0 is a smaller one of N1 and N2, and when N1=N2, N0=N1=N2.

### Claim 4 (depends on 2)

The display panel of claim 2, wherein:
|N1−N2|≥1.

### Claim 5 (depends on 1)

The display panel of claim 1, wherein:
a time interval from a beginning of the non-light-emitting stage to a beginning of the bias adjustment stage in the first frame is L3, and a time interval from a beginning of the non-light-emitting stage to a beginning of the bias adjustment stage in the second frame is L4, wherein L3>L4.

### Claim 6 (depends on 1)

The display panel of claim 1, wherein:
a brightness of the light-emitting element in the first mode is lower than a brightness of the light-emitting element in the second mode.

### Claim 7 (depends on 1)

The display panel of claim 1, wherein:
W1/L1<½, and/or W2/L2<½.

### Claim 8 (depends on 1)

The display panel of claim 1, wherein:
in the bias adjustment stage, the bias adjustment module is turned on, and the bias adjustment module is configured to provide the bias adjustment signal to the source or the drain of the driving transistor.

### Claim 9 (depends on 1)

A display device comprising the display panel of claim 1.

### Claim 10

A display panel comprising:
a pixel circuit including a driving module, a data writing module, a bias adjustment module, and a compensation module, the driving module including a driving transistor, the data writing module being configured to provide a data signal for the driving transistor, the bias adjustment module being configured to provide a bias adjustment signal for the driving transistor, and the compensation module being connected between a gate and a drain of the driving transistor; and
a light-emitting element;
wherein:
a time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, the non-light-emitting stage including a bias adjustment stage, the compensation module being turned off and at least one of a source or the drain of the driving transistor being configured to receive the bias adjustment signal in the bias adjustment stage;
an operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2;
L1>L2;
a working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame;
a time length of the bias adjustment stage in the first frame is W1, and a time length of the bias adjustment stage in the second frame is W2;
W2/W1≥1, and/or W2/W1<L1/L2.

### Claim 11 (depends on 10)

The display panel of claim 10, wherein:
the bias adjustment stage in the first frame includes N1 sub-bias adjustment stages, wherein N1≥1;
the bias adjustment stage in the second frame includes N2 sub-bias adjustment stages, wherein N2≥1; and
a time length of at least one sub-bias adjustment stage in the first frame is equal to a time length of at least one sub-bias adjustment stage in the second frame.

### Claim 12 (depends on 11)

The display panel of claim 11, wherein:
a time length of an ith sub-bias adjustment stage in the first frame is equal to a time length of an ith sub-bias adjustment stage in the second frame, wherein 1≤i≤N0; and
when N1≠N2, NO is a smaller one of N1 and N2, and when N1=N2, N0=N1=N2.

### Claim 13 (depends on 11)

The display panel of claim 11, wherein:
|N1−N2|≥1.

### Claim 14 (depends on 10)

The display panel of claim 10, wherein:
a time interval from a beginning of the non-light-emitting stage to a beginning of the bias adjustment stage in the first frame is L3, and a time interval from a beginning of the non-light-emitting stage to a beginning of the bias adjustment stage in the second frame is L4, wherein L3>L4.

### Claim 15 (depends on 10)

The display panel of claim 10, wherein:
a brightness of the light-emitting element in the first mode is lower than a brightness of the light-emitting element in the second mode.

### Claim 16 (depends on 10)

The display panel of claim 10, wherein:
W1/L1<½, and/or W2/L2<½.

### Claim 17 (depends on 10)

The display panel of claim 10, wherein:
in the bias adjustment stage, the bias adjustment module is turned on, the compensation module is turned off, and the bias adjustment module is configured to provide the bias adjustment signal to the source or the drain of the driving transistor.

### Claim 18 (depends on 10)

A display device comprising the display panel of claim 10.

### Claim 19

A display panel comprising:
a pixel circuit including a driving module, the driving module including a driving transistor; and
a light-emitting element;
wherein:
a time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, the non-light-emitting stage including a bias adjustment stage, at least one of a source or a drain of the driving transistor being configured to receive a bias adjustment signal in the bias adjustment stage;
an operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2;
L1>L2;
a working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame;
a time length of the bias adjustment stage in the first frame is W1, and a time length of the bias adjustment stage in the second frame is W2;
W2/W1≥1, and/or W2/W1<L1/L2.

### Claim 20 (depends on 19)

A display device comprising the display panel of claim 19.