# US 12,118,909 B2 · Gate drive circuit and display panel

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- Number: US 12,118,909 B2
- Document ID: US12118909B2
- Status: Granted
- Kind: B2
- Application number: 17/434,561
- Filed: 2021-06-18
- Published: 2024-01-18
- Granted: 2024-10-15
- Earliest claimed: 2021-06-08
- Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Inventors: Haiming Cao
- Web page: https://patentgrep.com/patent/US12118909B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2320/0252: Improving the response speed
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present application discloses a gate drive circuit and a display panel. The gate drive circuit includes a plurality of cascaded gate drive units, in which by adopting a same complex clock signal for a pull-down control module, a maintaining module and a pull-down module, a N-th-stage gate drive unit can rapidly pull down a falling edge of a N-th-stage scan signal to the potential of a constant low voltage level signal and effectively reduces the time required to pull down the N-th-stage scan signal from high voltage level to low voltage level.

## Claims

### Claim 1

A gate drive circuit, comprising a plurality of cascaded gate drive units, in which a N-th-stage gate drive unit comprises:
a pull-down control module, a control end of the pull-down control module configured to receive a complex clock signal, an output end of the pull-down control module electrically connected to a N-th-stage node, the complex clock signal comprising a first clock signal;
a pull-up module, the control end of the pull-up module electrically connected to the N-th-stage node, the output end of the pull-up module configured to output a N-th-stage scan signal;
a pull-down module, an input end of the pull-down module configured to receive a constant low voltage level signal, the output end of the pull-down module electrically connected to the output end of the pull-up module, the control end of the pull-down module configured to receive the first clock signal; and
a maintaining module, one of the input end and the output end of the maintaining module electrically connected to the N-th-stage node, the other one of the input end and the output end of the maintaining module electrically connected to the output end of the pull-up module, the control end of the maintaining module configured to receive the complex clock signal,
wherein the N-th-stage gate drive unit further comprises:
a pull-up control module, the input end of the pull-up control module level electrically connected to the input end of the pull-down control module, the control end of the pull-up control module electrically connected to a (N−4)-th-stage node, the output end of the pull-up control module electrically connected to the N-th-stage node.

### Claim 2 (depends on 1)

The gate drive unit of claim 1, wherein the N-th-stage gate drive unit further comprises:
a first abnormal power-off control module, the input end of the first abnormal power-off control module and the control end of the first abnormal power-off control module configured to receive a first global control signal, the output end of the first abnormal power-off control module electrically connected to the output end of the pull-up module; and
a second abnormal power-off control module, the input end of the second abnormal power-off control module configured to receive the constant low voltage level signal, the control end of the second abnormal power-off control module configured to receive the first global control signal, the output end of the second abnormal power-off control module electrically connected to the N-th-stage node.

### Claim 3 (depends on 1)

The gate drive unit of claim 1, wherein the N-th-stage gate drive unit further comprises:
a first reset module, the input end of the first reset module configured to receive the constant low voltage level signal, the control end of the first reset module configured to receive a reset signal, the output end of the first reset module electrically connected to the N-th-stage node; and
a second reset module, the input end of the second reset module configured to receive the constant low voltage level signal, the control end of the second reset module configured to receive the reset signal, the output end of the second reset module electrically connected to the output end of the pull-up module.

### Claim 4 (depends on 1)

The gate drive unit of claim 1, wherein the N-th-stage gate drive unit further comprises:
a voltage level coupling module, one end of the voltage level coupling module is electrically connected to the control end of the pull-up module and the other end of the voltage level coupling module electrically connected to the output end of the pull-up module.

### Claim 5 (depends on 4)

The gate drive unit of claim 4, wherein the N-th-stage gate drive unit further comprises:
a global control module, the input end of the global control module configured to receive the constant low voltage level signal, the control end of the global control module configured to receive a second global control signal, and the output end of the global control module electrically connected to the output end of the pull-up module.

### Claim 6 (depends on 1)

The gate drive circuit of claim 1, wherein the complex clock signal further comprises a second clock signal, and operation cycle of the first clock signal partially overlaps with operation cycle of the second clock signal.

### Claim 7 (depends on 1)

The gate drive circuit of claim 1, wherein the pull-down control module comprises:
a first thin-film transistor, a gate of the first thin-film transistor configured to receive the first clock signal, one of a source and a drain of the first thin-film transistor electrically connected to the N-th-stage node; and
a second thin-film transistor, one of the source and the drain of the second thin-film transistor electrically connected to the other one of the source and the drain electrode of the first thin-film transistor, the gate of the second thin-film transistors configured to receive a second clock signal.

### Claim 8 (depends on 7)

The gate drive circuit of claim 7, wherein the pull-up module comprises:
a third thin-film transistor, the gate of the third thin-film transistor electrically connected to the N-th-stage node, one of the source and the drain of the third thin-film transistor configured to output the N-th-stage scan signal.

### Claim 9 (depends on 8)

The gate drive circuit of claim 8, wherein the maintaining module comprises:
a fourth thin-film transistor, one of the source and the drain of the fourth thin-film transistor electrically connected to one of the source and the drain of the third thin-film transistor, the gate of the fourth thin-film transistor configured to receive the first clock signal; and
a fifth thin-film transistor, one of the source and the drain of the fifth thin-film transistor electrically connected to the other one of the source and the drain of the fourth thin-film transistor, the gate of the fifth thin-film transistor configured to receive the second clock signal, the other one of the source and the drain of the fifth thin-film transistor electrically connected to the N-th-stage node.

### Claim 10 (depends on 9)

The gate drive circuit of claim 9, wherein the pull-down module comprises:
a sixth thin-film transistor, one of the source and the drain of the sixth thin-film transistor configured to receive the constant low voltage level signal, the gate of the sixth thin-film transistor configured to receive the first clock signal, the other one of the source and the drain of the sixth thin-film transistor electrically connected to one of the source and the drain of the third thin-film transistor.

### Claim 11 (depends on 10)

The gate drive circuit of claim 10, wherein the pull-up module comprises:
a seventh thin-film transistor, one of the source and the drain of the seventh thin-film transistor electrically connected to one of the source and the drain of the second thin-film transistor, the gate of the seventh thin-film transistors electrically connected to a (N−4)-th-stage node, the other one of the source and the drain of the seventh thin-film transistor electrically connected to the N-th-stage node.

### Claim 12 (depends on 1)

A display panel, comprising the gate drive circuit according to claim 1.

### Claim 13

A gate drive circuit, comprising a plurality of cascaded gate drive units, in which a N-th-stage gate drive unit comprises:
a first thin-film transistor, a gate of the first thin-film transistor configured to receive a first clock signal, one of a source and a drain of the first thin-film transistor electrically connected to a N-th-stage node;
a second thin-film transistor, one of the source and the drain of the second thin-film transistor electrically connected to the other one of the source and the drain electrode of the first thin-film transistor, the gate of the second thin-film transistors configured to receive a second clock signal;
a third thin-film transistor, the gate of the third thin-film transistor electrically connected to the N-th-stage node, one of the source and the drain of the third thin-film transistor configured to output a N-th-stage scan signal;
a fourth thin-film transistor, one of the source and the drain of the fourth thin-film transistor electrically connected to one of the source and the drain of the third thin-film transistor, the gate of the fourth thin-film transistor configured to receive the first clock signal;
a fifth thin-film transistor, one of the source and the drain of the fifth thin-film transistor electrically connected to the other one of the source and the drain of the fourth thin-film transistor, the gate of the fifth thin-film transistor configured to receive the second clock signal, the other one of the source and the drain of the fifth thin-film transistor electrically connected to the N-th-stage node; and
a sixth thin-film transistor, one of the source and the drain of the sixth thin-film transistor configured to receive a constant low voltage level signal, the gate of the sixth thin-film transistor configured to receive the first clock signal, the other one of the source and the drain of the sixth thin-film transistor electrically connected to one of the source and the drain of the third thin-film transistor.

### Claim 14 (depends on 13)

The gate drive unit of claim 13, wherein the N-th-stage gate drive unit further comprises:
a seventh thin-film transistor, one of the source and the drain of the seventh thin-film transistor electrically connected to one of the source and the drain of the second thin-film transistor, the gate of the seventh thin-film transistors electrically connected to a (N−4)-th-stage node, the other one of the source and the drain of the seventh thin-film transistor electrically connected to the N-th-stage node.

### Claim 15 (depends on 13)

The gate drive unit of claim 13, wherein the N-th-stage gate drive unit further comprises:
an eighth thin-film transistor, the gate of the eighth thin-film transistor and one of the source and the drain of the eighth thin-film transistor configured to receive a first global control signal, the other one of the source and the drain of the eighth thin-film transistor electrically connected to one of the source and the drain of the third thin-film transistor; and
a ninth thin-film transistor, one of the source and the drain of the ninth thin-film transistor configured to receive the constant low voltage level signal, the gate of the ninth thin-film transistor configured to receive the first global control signal, and the other one of the source and the drain of the ninth thin-film transistor electrically connected to the N-th-stage node.

### Claim 16 (depends on 13)

The gate drive unit of claim 13, wherein the N-th-stage gate drive unit further comprises:
a tenth thin-film transistor, one of the source and the drain of the tenth thin-film transistor configured to receive the constant low voltage level signal, the gate of the tenth thin-film transistor configured to receive a reset signal, the other one of the tenth thin-film transistor electrically connected to the N-th-stage node; and
an eleventh thin-film transistor, one of the source and the drain of the eleventh thin-film transistor configured to receive the constant low voltage level signal, the gate of the eleventh thin-film transistor configured to receive the reset signal, the other one of the eleventh thin-film transistor electrically connected to one of the source and the drain of the third thin-film transistor.

### Claim 17 (depends on 13)

The gate drive unit of claim 13, wherein the N-th-stage gate drive unit further comprises:
a first capacitor, a first end of the first capacitor electrically connected to the N-th-stage node and a second end of the first capacitor electrically connected to one of the source and the drain of the third thin-film transistor.

### Claim 18 (depends on 17)

The gate drive unit of claim 17, wherein the N-th-stage gate drive unit further comprises:
a twelfth thin-film transistor, one of the source and the drain of the twelfth thin-film transistor configured to receive the constant low voltage level signal, the gate of the twelfth thin-film transistor configured to receive a second global control signal, and the other one of the twelfth thin-film transistor electrically connected to one of the source and the drain of the third thin-film transistor.

### Claim 19 (depends on 13)

The gate drive circuit of claim 13, wherein operation cycle of the first clock signal partially overlaps with operation cycle of the second clock signal.