# US 12,118,376 B2 · Virtual mode execution manager > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,118,376 B2 - Document ID: US12118376B2 - Status: Granted - Kind: B2 - Application number: 17/235,206 - Filed: 2021-04-20 - Published: 2022-10-20 - Granted: 2024-10-15 - Earliest claimed: 2021-04-20 - Assignees: STMicroelectronics International N.V.; STMicroeletronics Application GmbH - Applicants: STMicroelectronics International N.V.; STMicroelectronics Application GmbH - Inventors: Deepak Baranwal; Amritanshu Anand; Roberto Colombo; Boris Vittorelli - Web page: https://patentgrep.com/patent/US12118376B2 ## CPC - G06F 9/45558: {Hypervisor-specific management and integration aspects} - G06F 9/455: Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines - G06F 9/45533: {Hypervisors; Virtual machine monitors} - G06F 9/48: Program initiating; Program switching, e.g. by interrupt - G06F 9/4812: {by interrupt, e.g. masked} - G06F 9/4843: {by program, e.g. task dispatcher, supervisor, operating system} - G06F 9/485: {Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence)} - G06F 9/4856: {resumption being on a different machine, e.g. task migration, virtual machine migration (G06F9/5088 takes precedence)} - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/50: Allocation of resources, e.g. of the central processing unit [CPU] - G06F 9/5083: {Techniques for rebalancing the load in a distributed system} - G06F 9/5088: {involving task migration} - G06F 2009/4557: {Distribution of virtual machine instances; Migration and load balancing} - G06F 2009/45575: {Starting, stopping, suspending or resuming virtual machine instances} - G06F 2009/45579: {I/O management, e.g. providing access to device drivers or storage} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines. ## Claims ### Claim 1 A microcontroller, comprising: a microprocessor executing a plurality of virtual machines; virtual execution mode manager circuitry comprising a hardware device coupled to the microprocessor and configured to execute a state machine that generates interrupts to the microprocessor; a plurality of peripherals, with different ones of the plurality of virtual machines using different subsets of the plurality of peripherals during execution in different modes, the plurality of peripherals being hardware devices in bidirectional communication with the hardware device of the virtual execution mode manager circuitry; mode change logic circuitry configured to: receive a mode change request from the microprocessor, the mode change request indicating which of the plurality of virtual machines are to change execution mode and what execution modes those virtual machines are to change to; and send the mode change request to the virtual execution mode manager circuitry; and the virtual execution mode manager circuitry further configured to, for each virtual machine having its execution mode changed, send clock gate requests to the subset of the plurality of peripherals corresponding to the execution mode that virtual machine is to change to; wherein the subset the plurality of peripherals, in response to the clock gate requests, are configured to complete their current operations, enter into a clock-gated state, and send clock-gate acknowledgement signals to the virtual execution mode manager circuitry; wherein the virtual execution mode manager circuitry is further configured to, for each virtual machine having its execution mode changed, send a mode change acknowledgement to mode entry logic circuitry indicating that the execution mode of that virtual machine is ready to be changed; wherein the mode change logic circuitry is further configured to, for each virtual machine having its execution mode changed, change that virtual machine to the execution mode it is to change to, and send a mode change completion indication to the virtual execution mode manager circuitry; and wherein the virtual execution mode manager circuitry is further configured to, for each virtual machine whose execution mode has changed, generate an interrupt and send that interrupt to the microprocessor. ### Claim 2 (depends on 1) The microcontroller of claim 1, further comprising a set of registers within the virtual execution mode manager circuitry for each virtual machine storing indications of which subset of the plurality of peripherals are used in what execution modes; and wherein the virtual execution mode manager circuitry is configured to, for each virtual machine having its execution mode changed, read the registers corresponding to the execution mode that virtual machine is to be changed into so as to know which subset of the plurality of peripherals to send the clock gate request to. ### Claim 3 (depends on 1) The microcontroller of claim 1, further comprising a set of registers within the mode change logic circuitry for each virtual machine storing indications of which subset of the plurality of peripherals are used in what execution modes; wherein the mode change logic circuitry is configured to, for each virtual machine having its execution mode changed, read the registers corresponding to the execution mode that virtual machine is to be changed into and send data from those registers to the virtual execution mode manager circuitry so that the virtual execution mode manager circuitry knows which subset of the plurality of peripherals to send the clock gate request to. ### Claim 4 (depends on 1) The microcontroller of claim 1, wherein the mode entry logic circuitry is configured to, during changing virtual machines to the execution modes they are to be changed to, re-start the subsets of peripherals corresponding to those execution modes such that they switch back from the clock-gated state to an operational state. ### Claim 5 (depends on 1) The microcontroller of claim 1, wherein at least some of the plurality of virtual machines are executed on a single core of the microprocessor. ### Claim 6 (depends on 1) The microcontroller of claim 1, wherein the virtual execution mode manager circuitry is further configured to, for each virtual machine having its execution mode changed, send clock gate requests to a subset of the plurality of peripherals corresponding to the execution mode that virtual machine is currently in, at the same time as sending clock gate requests to the subset of the plurality of peripherals corresponding to the execution mode that the virtual machine is to switch to; and wherein the subsets the plurality of peripherals, in response to the sent clock gate requests, are configured to complete their current operations, enter into a clock-gated state, and send clock-gate acknowledgement signals to the virtual execution mode manager circuitry. ### Claim 7 (depends on 1) The microcontroller of claim 1, wherein the microprocessor includes a plurality of cores, with different cores executing different ones of the plurality of virtual machines; and wherein the virtual execution mode manager circuitry, for at least one virtual machine whose execution mode has been changed, sends the generated interrupt to the core executing that virtual machine. ### Claim 8 (depends on 1) The microcontroller of claim 1, wherein the microprocessor includes a plurality of cores, with different cores executing different ones of the plurality of virtual machines; and wherein the virtual execution mode manager circuitry, for at least one virtual machine whose execution mode has been changed, sends the generated interrupt to a core not executing that virtual machine. ### Claim 9 A method, comprising: executing a first virtual machine in a first execution mode on a microprocessor, the first virtual machine in the first execution mode using a first subset of a plurality of peripherals that are hardware devices; executing a second virtual machine in a second execution mode on the microprocessor, the second virtual machine in the second execution mode using a second subset of the plurality of peripherals; sending an indication to mode entry logic circuitry that the first virtual machine is to be changed to execute in a third execution mode, the third execution mode using a third subset of the plurality of peripherals; sending a mode change request from the mode entry logic circuitry to virtual execution mode manager circuitry embodied within a hardware device coupled to the microprocessor to execute a state machine generating interrupts to the microprocessor, and in bidirectional communication with the plurality of peripherals, the mode change request indicating that the first virtual machine is to change mode to the third execution mode; sending clock gate requests from the virtual execution mode manager circuitry to the third subset of the plurality of peripherals; in response to the third subset of the plurality of peripherals completing current tasks, placing the third subset into a clock-gated mode, and sending clock-gate acknowledgements back to the virtual execution mode manager circuitry; sending a mode change acknowledgement from the virtual execution mode manager circuitry to the mode entry logic circuitry indicating that the first virtual machine is ready to be changed to the third execution mode; changing the first virtual machine to the third execution mode; sending a mode change completed indication from the mode entry logic circuitry to the virtual execution mode manager circuitry to indicate that mode change is complete; and generating an interrupt in response to receipt of the mode change completed indication. ### Claim 10 (depends on 9) The method of claim 9, further comprising: sending clock gate requests from the virtual execution mode manager circuitry to the first subset of the plurality of peripherals at a same time as sending the clock gate requests to the third subset of the plurality of peripherals; and in response to the first subset of the plurality of peripherals completing current tasks, placing the first subset into a clock-gated mode, and sending clock-gate acknowledgements back to the virtual execution mode manager circuitry, prior to sending the mode change acknowledgement. ### Claim 11 (depends on 9) The method of claim 9, further comprising storing indications of which subset of the plurality of peripherals are to be used in what execution modes in a set of registers within the virtual execution mode manager circuitry, and for each virtual machine to have its execution mode changed, reading the registers corresponding to the execution mode that virtual machine is to be changed into so as to know which subset of the plurality of peripherals to send the clock gate request to. ### Claim 12 (depends on 9) The method of claim 9, further comprising storing indications of which subset of the plurality of peripherals are to be used in what execution modes in a set of registers within the mode entry logic circuitry, and, for each virtual machine to have its execution mode changed, reading the registers corresponding to the execution mode that virtual machine is to be changed into and send data from those registers to the virtual execution mode manager circuitry so that the virtual execution mode manager circuitry knows which subset of the plurality of peripherals to send the clock gate request to. ### Claim 13 (depends on 9) The method of claim 9, further comprising, during changing virtual machines to the execution modes they are to be changed to, re-starting the subsets of peripherals corresponding to those execution modes such that they switch back from the clock-gated state to an operational state. ### Claim 14 (depends on 9) The method of claim 9, wherein the first and second virtual machines are executed on different cores of a same microprocessor and the core executing the first virtual machine receives the interrupt. ### Claim 15 (depends on 9) The method of claim 9, wherein the first and second virtual machines are executed on different cores of a same microprocessor and the core executing the second virtual machine receives the interrupt. ### Claim 16 A microcontroller, comprising: a microprocessor executing a plurality of virtual machines; virtual execution mode manager circuitry comprising a hardware device coupled to the microprocessor and configured to execute a state machine that generates interrupts to the microprocessor; a plurality of peripherals, with different ones of the plurality of virtual machines using different subsets of the plurality of peripherals during execution in different modes modes, the plurality of peripherals being hardware devices in bidirectional communication with the hardware device of the virtual execution mode manager circuitry; mode change logic circuitry configured to: receive a mode change request from the microprocessor, the mode change request indicating which of the plurality of virtual machines are to change execution mode; and send the mode change request to the virtual execution mode manager circuitry; and the virtual execution mode manager circuitry configured to, for each virtual machine having its execution mode changed, send clock gate requests to the subset of the plurality of peripherals corresponding to that virtual machine; wherein the subset the plurality of peripherals, in response to the clock gate requests, are configured to complete their current operations, enter into a clock-gated state, and send clock-gate acknowledgement signals to the virtual execution mode manager circuitry; wherein the virtual execution mode manager circuitry is further configured to, for each virtual machine having its execution mode changed, send a mode change acknowledgement to the mode entry logic circuitry indicating that the execution mode of that virtual machine is ready to be changed; wherein the mode change logic circuitry is further configured to, for each virtual machine having its execution mode changed, change the execution mode of that virtual machine, and send a mode change completion indication to the virtual execution mode manager circuitry; and wherein the virtual execution mode manager circuitry is further configured to, for each virtual machine whose execution mode has changed, generate an interrupt. ### Claim 17 (depends on 16) The microcontroller of claim 16, further comprising a set of registers within the virtual execution mode manager circuitry for each virtual machine storing indications of which subset of the plurality of peripherals are used in what execution modes; and wherein the virtual execution mode manager circuitry is configured to, for each virtual machine having its execution mode changed, read the corresponding registers. ### Claim 18 (depends on 16) The microcontroller of claim 16, wherein the mode entry logic circuitry is configured to, during changing execution modes of the virtual machines, re-starting the subsets of peripherals corresponding to those virtual machines such that they switch back from the clock-gated state to an operational state. ### Claim 19 (depends on 16) The microcontroller of claim 16, wherein at least some of the plurality of virtual machines are executed on a single core of the microprocessor. ### Claim 20 (depends on 16) The microcontroller of claim 16, wherein the virtual execution mode manager circuitry is further configured to, for each virtual machine having its execution mode changed, send clock gate requests to a subset of the plurality of peripherals corresponding to an execution mode that virtual machine is currently in, at the same time as sending clock gate requests to the subset of the plurality of peripherals corresponding to an execution mode that the virtual machine is to switch to; and wherein the subsets the plurality of peripherals, in response to the sent clock gate requests, are configured to complete their current operations, enter into a clock-gated state, and send clock-gate acknowledgement signals to the virtual execution mode manager circuitry. ### Claim 21 (depends on 16) The microcontroller of claim 16, wherein the microprocessor includes a plurality of cores, with different cores executing different ones of the plurality of virtual machines; and wherein the virtual execution mode manager circuitry, for at least one virtual machine whose execution mode has been changed, sends the generated interrupt to the core executing that virtual machine. ### Claim 22 (depends on 16) The microcontroller of claim 16, wherein the microprocessor includes a plurality of cores, with different cores executing different ones of the plurality of virtual machines; and wherein the virtual execution mode manager circuitry, for at least one virtual machine whose execution mode has been changed, sends the generated interrupt to a core not executing that virtual machine.