# US 12,118,356 B1 · Multi-threading processor and operating method thereof

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- Number: US 12,118,356 B1
- Document ID: US12118356B1
- Status: Granted
- Kind: B1
- Application number: 18/643,178
- Filed: 2024-04-23
- Granted: 2024-10-15
- Earliest claimed: 2023-07-18
- Assignees: MetisX CO., Ltd.
- Applicants: MetisX CO., Ltd.
- Inventors: Kwang Sun Lee; Do Hun Kim; Kee Bum Shin
- Web page: https://patentgrep.com/patent/US12118356B1

## CPC

- G06F 9/3009: {Thread control instructions}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/38: Concurrent instruction execution, e.g. pipeline or look ahead
- G06F 9/3824: {Operand accessing}
- G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A multi-threading processor is provided, which includes a cache including a memory and a controller, and a core electrically connected to the cache and configured to simultaneously execute and manage a plurality of threads, in which the core is configured to determine an occurrence of a data hazard for the plurality of threads and stall operations of the plurality of threads, receive, from the cache, hint information instructing a first thread of the plurality of threads to operate, and initiate an operation of the first thread based on the hint information while the data hazard for the plurality of threads is maintained.

## Claims

### Claim 1

A multi-threading processor comprising:
a cache including a memory and a controller; and
a core electrically connected to the cache and configured to simultaneously execute and manage a plurality of threads,
wherein the core is configured to:
determine an occurrence of a data hazard for the plurality of threads and stall operations of the plurality of threads;
receive, from the cache, hint information instructing a first thread of the plurality of threads to operate; and
initiate an operation of the first thread based on the hint information while the data hazard for the plurality of threads is maintained,
wherein the core transfers a data access request including address information to the cache, and
wherein the controller of the cache is configured to:
search a cache tag based on the address information to determine whether data corresponding to the address information is stored in the memory; and
transfer the hint information to the core in response to determining that the data corresponding to the address information is stored in the memory.

### Claim 2 (depends on 1)

The multi-threading processor according to claim 1, wherein the core is further configured to:
receive the hint information in n-th clock cycle; and
cause the first thread to initiate a fetch operation in (n+1)th clock cycle.

### Claim 3 (depends on 1)

The multi-threading processor according to claim 1, wherein the core is further configured to:
receive the hint information in n-th clock cycle;
resolve the data hazard in m-th clock cycle; and
cause the first thread to initiate a fetch operation in any one of (n+1)th clock cycle to (m−1)th clock cycle.

### Claim 4 (depends on 1)

The multi-threading processor according to claim 1, wherein the core is further configured to:
receive the hint information in n-th clock cycle;
resolve the data hazard in m-th clock cycle;
cause the first thread to perform a fetch operation and a decode operation from (n+1)th clock cycle to (m−1)th clock cycle; and
cause the first thread to perform an execution operation in the m-th clock cycle.

### Claim 5 (depends on 1)

The multi-threading processor according to claim 1, wherein the controller of the cache is further configured to:
transfer data corresponding to the address information to the core in m-th clock cycle; and
transfer the hint information to the core a predetermined clock cycle before the m-th clock cycle.

### Claim 6 (depends on 1)

The multi-threading processor according to claim 1, wherein the data access request includes information on the first thread, and
the hint information includes information on the first thread.

### Claim 7 (depends on 1)

The multi-threading processor according to claim 1, wherein the core includes a hazard controller configured to receive the hint information and initiate the operation of the first thread, and
wherein the hazard controller receives the hint information through a signal line connecting the core and the cache.

### Claim 8 (depends on 1)

The multi-threading processor according to claim 1, wherein the core is further configured to determine a resolution of the data hazard after initiating the operation of the first thread.

### Claim 9 (depends on 1)

The multi-threading processor according to claim 1, wherein the core is a multi-threading scalar core.

### Claim 10 (depends on 1)

The multi-threading processor according to claim 1, wherein the core is further configured to determine that the data hazard is occurred when the plurality of threads access a shared variable or bring different instructions.

### Claim 11

An operating method of a multi-threading processor comprising a cache including a memory and a controller, and a core electrically connected to the cache and configured to simultaneously execute and manage a plurality of threads, the method comprising:
determining, by the core, an occurrence of a data hazard for the plurality of threads and stalling operations of the plurality of threads;
receiving from the cache, by the core, hint information instructing a first thread of the plurality of threads to operate; and
initiating, by the core, an operation of the first thread based on the hint information while the data hazard for the plurality of threads is maintained,
wherein the receiving the hint information includes:
transferring, by the core, a data access request including address information to the cache; and
searching, by the controller of the cache, a cache tag based on the address information to determine whether data corresponding to the address information is stored in the memory, and transferring the hint information to the core in response to determining that the data corresponding to the address information is stored in the memory.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the receiving the hint information includes receiving the hint information in n-th clock cycle, and
wherein the initiating the operation of the first thread includes causing the first thread to initiate a fetch operation in (n+1)th clock cycle.

### Claim 13 (depends on 11)

The method according to claim 11, further comprising resolving the data hazard in m-th clock cycle,
wherein the receiving the hint information includes receiving the hint information in n-th clock cycle, and
the initiating the operation of the first thread includes causing the first thread to initiate a fetch operation in any one of (n+1)th clock cycle to (m−1)th clock cycle.

### Claim 14 (depends on 11)

The method according to claim 11, further comprising resolving the data hazard and performing, by the first thread, an execution operation in m-th clock cycle,
wherein the receiving the hint information includes receiving the hint information in n-th clock cycle, and
wherein the initiating the operation of the first thread includes causing the first thread to perform a fetch operation and a decode operation from (n+1)th clock cycle to (m−1)th clock cycle.