# US 12,118,333 B2 · Semiconductor device

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- Number: US 12,118,333 B2
- Document ID: US12118333B2
- Status: Granted
- Kind: B2
- Application number: 17/050,359
- Filed: 2019-04-15
- Published: 2021-10-14
- Granted: 2024-10-15
- Earliest claimed: 2018-04-26
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Takayuki Ikeda; Roh Yamamoto; Shuichi Katsui
- Web page: https://patentgrep.com/patent/US12118333B2

## CPC

- G06F 7/60: Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations {, e.g. using difunction pulse trains, STEELE computers, phase computers (conversion of digital data to or from non-denominational form H03M5/00, H03M7/00)}
- G06F 7/57: Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)}
- G06N 3/048: Activation functions
- G06N 3/0499: Feedforward networks
- G06N 3/065: Analogue means
- G06N 3/08: Learning methods
- G06N 3/09: Supervised learning
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device that updates a weight coefficient used for arithmetic operation by an artificial neural network is provided. Each of the first to third memory cells draws a current corresponding to data of its retention node and changes the data in accordance with the potentials of first and second wirings. When a weight coefficient and first and second reference data are held in the retention nodes of the first to third memory cells, the first circuit supplies, to a third wiring, a constant currents drawn by the second and third memory cells. When input data is input to the first wiring, a difference current between the constant current and a current drawn by the first memory cell is changed, and the second circuit outputs arithmetic result data corresponding to the change. The third circuit inputs update data corresponding to the arithmetic result data to the second wiring.

## Claims

### Claim 1

A semiconductor device comprising:
a first circuit configured to perform first arithmetic operation using a first data and a second data according to a predetermined formula, in order to output a first result;
a second circuit configured to output a first potential using a first current corresponding to the first result;
a third circuit configured to perform second arithmetic operation using the first result, the second data, and teacher data, and to output a second potential corresponding to a second result of the second arithmetic operation; and
a first memory cell electrically connected to the third circuit, the first memory cell storing a third potential,
a second memory cell electrically connected to the first circuit, the second memory cell configured to store a fourth potential corresponding to the first data,
a third memory cell electrically connected to the first circuit and the third circuit, the third memory cell configured to store a fifth potential corresponding to the second data,
wherein the teacher data is data input from outside to the third circuit,
wherein the first circuit is configured to output the first current into the second circuit,
wherein the third circuit is configured to receive the first potential output from the second circuit,
wherein the first result is a result of the first arithmetic operation using the first data and the second data, and
wherein the second result is configured to be input to the third memory cell to update the second data.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the second memory cell comprises a plurality of nodes storing a plurality of first potentials independently,
wherein the third memory cell comprises a plurality of nodes storing a plurality of second potentials independently, and
wherein the third circuit is configured to output results of arithmetic operation substituting a data corresponding each of the plurality of first potentials and a data corresponding to each of the plurality of second potentials respectively, using the value corresponding to the third potential.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the second arithmetic operation is performed a plurality of times to obtain the updated result.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the third circuit comprises an integrator circuit.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4,
wherein the second arithmetic operation is performed a plurality of times, and
wherein the integrator circuit output a total of the second arithmetic operation performed the plurality of times.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1,
wherein the second circuit comprises a comparator and a resistor,
wherein one of an inverting input terminal and a non-inverting input terminal of the comparator is electrically connected to the resistor, and
wherein an output terminal of the comparator is electrically connected to the third circuit.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1,
wherein the first memory cell comprises a first transistor, a second transistor, a first capacitor and a second capacitor,
wherein a first terminal of the first transistor is electrically connected to each of a gate of the second transistor, a first terminal of the first capacitor and a first terminal of the second capacitor, and
wherein a first terminal of the second transistor is configured to output the first current.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the first transistor and the second transistor overlap each other.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein each of the first transistor and the second transistor comprises a metal oxide in a channel formation region.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1,
wherein the first circuit comprises:
a first wiring configured to flow the first current;
a constant current circuit configured to supply current into the first wiring; and
a current sink circuit configured to draw or supply a current from the first wiring.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein each of the first circuit, the second circuit and the third circuit is a single-polarity circuit.

### Claim 12

A semiconductor device comprising:
a first circuit electrically connected to a first memory cell through a first wiring;
a second circuit electrically connected to the first circuit through the first wiring; and
a third circuit electrically connected to the first memory cell through a second wiring,
wherein the third circuit is electrically connected to the first memory cell through a third wiring,
wherein the third circuit comprises an input terminal,
wherein the first memory cell comprises a retention node,
wherein the first memory cell is configured to change a potential of the retention node of the first memory cell in accordance with a change in a potential of the second wiring,
wherein the first memory cell is configured to change the potential of the retention node of the first memory cell in accordance with a change in a potential of the third wiring,
wherein the first memory cell is configured to make a current corresponding to the potential of the retention node of the first memory cell flow between the first memory cell and the first wiring,
wherein the first circuit is configured to supply a current to the first wiring,
wherein the second circuit is configured to generate a first potential corresponding to a first current that flows between the first wiring and the second circuit and to output the first potential to the third circuit,
wherein a second potential is input to the input terminal of the third circuit, and
wherein the third circuit is configured to change the potential of the third wiring by the first potential, the second potential, and the potential of the second wiring.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12,
wherein the third circuit comprises an integrator circuit, and
wherein an output terminal of the integrator circuit is electrically connected to the third wiring.

### Claim 14 (depends on 12)

The semiconductor device according to claim 12,
wherein the second circuit comprises a comparator, a resistor and a first switch,
wherein one of an inverting input terminal and a non-inverting input terminal of the comparator is electrically connected to the resistor,
wherein the one of the inverting input terminal and the non-inverting input terminal of the comparator is electrically connected to the first wiring through the first switch, and
wherein an output terminal of the comparator is electrically connected to the third circuit.

### Claim 15 (depends on 12)

The semiconductor device according to claim 12,
wherein the first circuit comprises:
a first constant current circuit configured to supply current to the first wiring;
a second constant current circuit configured to supply current to the first wiring; and
a current sink circuit configured to draw current from the first constant current circuit or to draw current from the first wiring.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15,
wherein the first constant current circuit is configured to generate a second current that flows from the first circuit to the first wiring, as a constant current, when a first retention potential is held in the retention node of the first memory cell, a first initial potential is input from the second wiring, and a second initial potential is input from the third wiring,
wherein the second constant current circuit is configured to generate a third current that flows from the first circuit to the first wiring, as the constant current, when the first retention potential is held in the retention node of the first memory cell, a third potential is input from the second wiring, and the second initial potential is input from the third wiring,
wherein the current sink circuit is configured to draw the second current that flows from the first constant current circuit, as the constant current, when the first retention potential is held in the retention node of the first memory cell, the third potential is input from the second wiring, and the second initial potential is input from the third wiring,
wherein the first constant current circuit is configured to generate a fourth current that flows from the first circuit to the first wiring, as the constant current, when a second retention potential is held in the retention node of the first memory cell, the first initial potential is input from the second wiring, and the second initial potential is input from the third wiring,
wherein the first memory cell is configured to make a fifth current corresponding to the second retention potential, the third potential, and the second initial potential flow between the first memory cell and the first wiring, when the second retention potential is held in the retention node of the first memory cell, the third potential is input from the second wiring, and the second initial potential is input from the third wiring,
wherein the first circuit is configured to make a sum of the second to fourth currents generated by the first constant current circuit, the second constant current circuit, and the current sink circuit flow through the first wiring, when the second retention potential is held in the retention node of the first memory cell, the third potential is input from the second wiring, and the second initial potential is input from the third wiring,
wherein the first current is a difference current between the fifth current and a sum of the second current, the third current and the fourth current, and
wherein the third circuit is configured to change the second initial potential of the third wiring to a fourth potential corresponding to the first potential, the second potential, and a potential difference between the first initial potential of the second wiring and the third potential.

### Claim 17 (depends on 16)

The semiconductor device according to claim 16,
wherein a difference between the first retention potential and the second retention potential is a potential difference corresponding to first data,
wherein a difference between the first initial potential and the third potential is a potential difference corresponding to second data,
wherein the first current is a current corresponding to a product of the first data and the second data, and
wherein the second potential is a potential corresponding to the teacher data, and a difference between the second initial potential and the fourth potential is a potential difference corresponding to update data.

### Claim 18 (depends on 17)

The semiconductor device according to claim 17, further comprising:
a plurality of the first memory cells each electrically connected to the first wiring; and
a plurality of the third circuits,
wherein each of the plurality of first memory cells is electrically connected to the first wiring,
wherein each of the plurality of third circuits is electrically connected to one of the plurality of first memory cells through one of a plurality of second wirings,
wherein each of the plurality of third circuits is electrically connected to one of the plurality of first memory cells through one of a plurality of third wirings,
wherein each retention node of the plurality of first memory cells stores a potential difference corresponding to each of a plural pieces of the first data,
wherein each of potential differences corresponding to a plural pieces of the second data is applied to each of the plurality of second wirings,
wherein the first current is a current corresponding to a product-sum of the plural pieces of first data and the plural pieces of the second data, and
wherein the plurality of third circuits is configured to output potential differences corresponding to a plural pieces of the update data to the plurality of third wirings.

### Claim 19 (depends on 12)

The semiconductor device according to claim 12,
wherein the first memory cell comprises a first transistor, a second transistor, a first capacitor, and a second capacitor,
wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor, a first terminal of the first capacitor, and a first terminal of the second capacitor,
wherein a second terminal of the first capacitor is electrically connected to the second wiring,
wherein a second terminal of the second capacitor is electrically connected to the third wiring, and
wherein a first terminal of the second transistor is electrically connected to the first wiring.

### Claim 20 (depends on 12)

The semiconductor device according to claim 12,
wherein a channel formation region of each of the first transistor and the second transistor comprises a metal oxide, and
wherein each of the first circuit, the second circuit and the third circuit is a single-polarity circuit.