# US 12,118,332 B2 · Execution circuitry for floating-point power operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,118,332 B2 - Document ID: US12118332B2 - Status: Granted - Kind: B2 - Application number: 18/045,577 - Filed: 2022-10-11 - Published: 2024-03-21 - Granted: 2024-10-15 - Earliest claimed: 2022-09-20 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Ali Sazegari; Segev Elmalem; O-Cheng Chang; Jingwei Zhang; Ido Soffair; Aaftab A. Munshi - Web page: https://patentgrep.com/patent/US12118332B2 ## CPC - G06F 7/552: Powers or roots {, e.g. Pythagorean sums} - G06F 7/483: Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} - G06F 7/556: Logarithmic or exponential functions - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques are disclosed relating to dedicated power function circuitry for a floating-point power instruction. In some embodiments, execution circuitry is configured to execute a floating-point power instruction to evaluate the power function xy as 2y log2x. In some embodiments, base-2 logarithm circuitry is configured to evaluate a base-2 logarithm for a first input (e.g., log2 x) by determining coefficients for a polynomial function and evaluating the polynomial function using the determined coefficients and the first input. In some embodiments, multiplication circuitry multiplies the base-2 logarithm result by a second input to generate a multiplication result. In some embodiments, base-2 power function circuitry is configured to evaluate a base-2 power function for the multiplication result. Disclosed techniques may advantageously increase performance and reduce power consumption of floating-point power function operations with reasonable area and accuracy, relative to traditional techniques. ## Claims ### Claim 1 An apparatus, comprising: execution pipeline circuitry configured to, for execution of a single floating-point power instruction, operate on first and second floating-point inputs in a first floating-point format to generate a result that evaluates 2(second input*log 2(first input)), wherein the execution pipeline circuitry includes: a first pipeline portion having one or more stages that includes base-2 logarithm circuitry configured to evaluate the base-2 logarithm of the first input, including to: determine coefficients for a polynomial function based on the first input; and evaluate the polynomial function to determine a first result in a second floating-point format, based on the determined coefficients and the first input; a second pipeline portion configured to operate on results from the first pipeline portion, including multiplication circuitry configured to receive the first result from the base-2 logarithm circuitry and configured to: multiply the received first result by the second floating-point input to generate a multiplication result; wherein the second floating-point format includes a head component and a tail component, the multiplication is a head-tail operation, the multiplication result includes a head result and a tail result; and wherein the first floating-point format is an N-bit floating-point format; and the head result, and tail result are each represented using N bits or less; and a third pipeline portion configured to operate on results from the second pipeline portion, including base-2 power function circuitry configured to receive the multiplication result from the multiplication circuitry and configured to: evaluate two to the power of a representation of the multiplication result to generate a result of the single floating-point power instruction in the first floating-point format. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising: conversion circuitry configured to convert the head result and the tail result to the first floating-point format to generate a converted multiplication result; wherein the base-2 power function circuitry is configured to evaluate two to the power of the converted multiplication result. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the polynomial function is a third order polynomial and wherein, to determine coefficients for the third order polynomial, the base-2 logarithm circuitry is further configured to access a polynomial coefficient table based on the first input. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein one or more of the determined coefficients include head and tail components and one or more of the determined coefficients use a non-head-tail representation. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein a given entry of the polynomial coefficient table includes multiple coefficients for the third order polynomial corresponding to a range of input values. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the polynomial coefficient table is generated using overlapping intervals such that coefficients for a given entry in the polynomial coefficient table correspond to curve fitting over a greater range of input values than a range of input values corresponding to the entry. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein to evaluate two to the power of a representation of the multiplication result the base-2 power function circuitry is configured to: determine coefficients for a third order polynomial function based on the multiplication result; and evaluate the third order polynomial function to determine two to the power of a representation of the multiplication result in the first floating-point format. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the execution pipeline circuitry is further configured to execute a base-2 logarithm instruction, including to evaluate the base-2 logarithm of an input using the base-2 logarithm circuitry to generate a result of the base-2 logarithm instruction; and wherein the execution pipeline circuitry includes multiplexor circuitry configured to select the result of the base-2 logarithm instruction from the base-2 logarithm circuitry. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the execution pipeline circuitry is further configured to execute a base-2 power instruction, including to evaluate the base-2 power function of an input using the base-2 power function circuitry to generate a result of the base-2 power instruction; and wherein the execution pipeline circuitry includes multiplexor circuitry configured to select the result of the base-2 power instruction from the base-2 power function circuitry. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the apparatus is a computing device that further includes: a display; a central processing unit; and network interface circuitry. ### Claim 11 A method, comprising: executing, by pipeline circuitry of a computing device, a single floating-point power instruction that operates on first and second floating-point inputs in a first floating-point format to generate a result that evaluates 2(second input*log 2(first input)), wherein the executing includes: a first pipeline portion determining coefficients for a polynomial function based on the first input; the first pipeline portion evaluating the polynomial function to determine a first result in a second floating-point format, based on the determined coefficients and the first input; a second pipeline portion operating on results from the first pipeline portion, including receiving the first result and multiplying the first result by the second floating-point input to generate a multiplication result, wherein the second floating-point format includes a head component and a tail component, the multiplication is a head-tail operation, the multiplication result includes a head result and a tail result, the first floating-point format is an N-bit floating-point format, and the head result, and tail result are each represented using N bits or less; and a third pipeline portion operating on results from the second pipeline portion, including receiving the multiplication result and evaluating two to the power of a representation of the multiplication result to generate a result of the single floating-point power function in the first floating-point format. ### Claim 12 (depends on 11) The method of claim 11, wherein the polynomial function is a third order polynomial and wherein, to determine coefficients for the third order polynomial includes accessing a polynomial coefficient table based on the first input. ### Claim 13 (depends on 12) The method of claim 12, wherein one or more of the determined coefficients include head and tail components and one or more of the determined coefficients use a non-head-tail representation. ### Claim 14 A non-transitory computer-readable medium having instructions stored thereon that are executable by a computing device to perform operations comprising: executing, by pipeline circuitry of the computing device, a single floating-point power instruction of the instructions to operate on first and second floating-point inputs in a first floating-point format to generate a result that evaluates 2(second input*log 2(first input)), wherein the executing includes: a first pipeline portion evaluating a base-2 logarithm of the first input, including to determine coefficients for a polynomial function based on the first input and evaluate the polynomial function to determine a first result in a second floating-point format, based on the determined coefficients and the first input; a second pipeline portion operating on results from the first pipeline portion, including receiving the first result and multiplying the first result by the second floating-point input to generate a multiplication result, wherein the second floating-point format includes a head component and a tail component, the multiplication is a head-tail operation, the multiplication result includes a head result and a tail result, the first floating-point format is an N-bit floating-point format, and the head result, and tail result are each represented using N bits or less; and a third pipeline portion operating on results from the second pipeline portion, including receiving the multiplication result and evaluating two to the power of a representation of the multiplication result to generate a result of the single floating-point power instruction in the first floating-point format. ### Claim 15 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the executing further includes: converting the head result and the tail result to the first floating-point format to generate a converted multiplication result. ### Claim 16 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the executing further includes: determining coefficients for a third order polynomial function to evaluate the base-2 logarithm of the first input, wherein the determining includes accessing a polynomial coefficient table based on the first input.