# US 12,118,327 B1 · Ripple carry adder with inverted ferroelectric or paraelectric based adders

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,118,327 B1
- Document ID: US12118327B1
- Status: Granted
- Kind: B1
- Application number: 17/467,061
- Filed: 2021-09-03
- Granted: 2024-10-15
- Earliest claimed: 2021-09-02
- Assignees: Kepler Computing Inc.
- Applicants: Kepler Computing Inc.
- Inventors: Amrita Mathuriya; Ikenna Odinaka; Rajeev Kumar Dokania; Rafael Rios; Sasikanth Manipatruni
- Web page: https://patentgrep.com/patent/US12118327B1

## CPC

- G06F 7/503: using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
- G06F 7/501: Half or full adders, i.e. basic adder cells for one denomination
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/2275: {Writing or programming circuits or methods}
- H03K 19/18: using galvano-magnetic devices, e.g. Hall-effect devices
- H03K 19/23: Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
- H10D 1/682: {having dielectrics comprising perovskite structures}
- G06F 2207/4822: Majority gates
- H10D 1/694: {comprising noble metals or noble metal oxides}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

## Claims

### Claim 1

An apparatus comprising:
a first 1-bit adder to receive a first input, a second input, and a third input, wherein the first input is a first operand, wherein the second input is a second operand, wherein the third input is a carry-in input, wherein the third input is coupled to ground, and wherein the first 1-bit adder is to generate a first inverted sum output and a first inverted carry output; and
a second 1-bit adder coupled to the first 1-bit adder, wherein the second 1-bit adder is to receive a fourth input, a fifth input, and a sixth input, wherein the fourth input is a third operand, wherein the fifth input is a fourth operand, and wherein the sixth input is an inverted carry-in input, wherein the sixth input is coupled to the first inverted carry output, wherein the second 1-bit adder is to generate a second sum output and a second carry output, wherein individual ones of the first 1-bit adder and the second 1-bit adder include at least three input capacitors with non-linear polar material, wherein first terminals of the at least three input capacitors are directly connected without magnets to at least three inputs of the individual ones of the first 1-bit adder and the second 1-bit adder, and wherein second terminals of the at least three input capacitors are directly connected without magnets to a node.

### Claim 2 (depends on 1)

The apparatus of claim 1 further comprising a first inverter to generate the third operand for the fourth input, and a second inverter to generate the fourth operand for the fifth input.

### Claim 3 (depends on 1)

The apparatus of claim 1 further comprising a third inverter to invert the first inverted sum output to generate a first sum output.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the sixth input is either directly coupled to the first inverted carry output or receives a buffered version of the first inverted carry output.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the first 1-bit adder comprises:
a 3-input minority gate to receive the first input, the second input, and the third input; and
a 5-input minority gate to receive the first input, the second input, the third input, and two times an output of the 3-input minority gate, wherein the 3-input minority gate and the 5-input minority gate include the non-linear polar material.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the output of the 3-input minority gate is the first inverted carry output, and wherein an output of the 5-input minority gate is the first inverted sum output.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the 3-input minority gate comprises:
a first capacitor to receive the first input, the first capacitor is directly connected to the node;
a second capacitor to receive the second input, the second capacitor is directly connected to the node; and
a third capacitor to receive the third input, wherein the third capacitor is directly connected to the node, wherein the first capacitor, the second capacitor, and the third capacitor include the non-linear polar material, and wherein the at least three input capacitors include the first capacitor, the second capacitor, and the third capacitor.

### Claim 8 (depends on 5)

The apparatus of claim 5, wherein the 5-input minority gate comprises:
a first capacitor to receive the first input, wherein the first capacitor is directly connected without magnets to the node;
a second capacitor to receive the second input, wherein the second capacitor is directly connected without magnets to the node;
a third capacitor to receive the third input, wherein the third capacitor is directly connected without magnets to the node;
a fourth capacitor to receive the output of the 3-input minority gate, wherein the fourth capacitor is directly connected without magnets to the node; and
a fifth capacitor to receive the output of the 3-input minority gate, wherein the fifth capacitor is directly connected without magnets to the node, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor include the non-linear polar material, and wherein the at least three input capacitors include the first capacitor, the second capacitor, and the third capacitor.

### Claim 9 (depends on 1)

The apparatus of claim 1, the second 1-bit adder comprises:
a 3-input minority gate to receive the fourth input, the fifth input, and the sixth input, wherein the fourth input receives an inverted fourth input, wherein the fifth input receives an inverted fifth input, and wherein the sixth input is an inverted sixth input; and
a 5-input minority gate to receive the fourth input, the fifth input, the sixth input, and two times an output of the 3-input minority gate, wherein the 3-input minority gate and the 5-input minority gate include the non-linear polar material.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the non-linear polar material includes one of: a ferroelectric material, a paraelectric material, or a non-linear dielectric.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the ferroelectric material includes one of:
bismuth ferrite (BFO) with a first doping material, wherein the first doping material is one of lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a perovskite which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3;
a first hexagonal ferroelectric which includes one of: YMnO3 or LuFeO3;
a second hexagonal ferroelectric of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides or their alloyed oxides;
hafnium oxides as Hf(1-x) Ex Oy, where E includes one of Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, wherein x and y are first and second fractions, respectively;
Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-x-y)Mg(x)Nb(y)N, wherein x and y are second fractions, respectively;
HfO2 doped with one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
niobate type compounds LiNbO3, LiTaO3, lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or
an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 and 100.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein the paraelectric material includes one of SrTiO3, TiO3 with Ba and Sr, HfZrO2, Hf—Si—O, La-substituted PbTiO3, or PMN-PT based relaxor ferroelectrics.

### Claim 13

An apparatus comprising:
a ripple carry adder comprising alternating adders, wherein the alternating adders include:
a first 1-bit adder with inverted carry output and inverted sum output, and
a second 1-bit adder with inverted carry input and inverted operands,
wherein the inverted carry output is coupled to the inverted carry input; and
an inverter coupled to the inverted sum output of the first 1-bit adder, wherein the alternating adders include majority or minority gates, wherein an individual majority or minority gate includes at least three capacitors, wherein first terminals of the at least three capacitors are directly connected without magnets to at least three inputs of the individual majority or minority gate, wherein second terminals of the at least three capacitors are directly connected without magnets to a node, and wherein the at least three capacitors include non-linear polar material.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the first 1-bit adder and the second 1-bit adder include the non-linear polar material.

### Claim 15 (depends on 13)

The apparatus of claim 13, wherein the first 1-bit adder comprises:
a 3-input minority gate to receive a first input, a second input, and a third input; and
a 5-input minority gate to receive the first input, the second input, the third input, and two times an output of the 3-input minority gate, wherein the 3-input minority gate and the 5-input minority gate include the non-linear polar material.

### Claim 16 (depends on 13)

The apparatus of claim 13, wherein the second 1-bit adder comprises:
a 3-input minority gate to receive a fourth input, a fifth input, and a sixth input, wherein the fourth input receives an inverted fourth input, wherein the fifth input receives an inverted fifth input, and wherein the sixth input is the inverted carry output from the first 1-bit adder; and
a 5-input minority gate to receive the fourth input, the fifth input, the sixth input, and two times an output of the 3-input minority gate, wherein the 3-input minority gate and the 5-input minority gate include the non-linear polar material.

### Claim 17

A system comprising:
a processor circuitry to execute one or more instructions;
a communication interface communicatively coupled to the processor circuitry; and
a memory coupled to the processor circuitry, wherein the processor circuitry includes:
a ripple carry adder comprising alternating adders, wherein the alternating adders include:
a first 1-bit adder with inverted carry output and inverted sum output, and
a second 1-bit adder with inverted carry input and inverted operands, wherein the inverted carry output is coupled to the inverted carry input, wherein the alternating adders include majority or minority gates, wherein an individual majority or minority gate includes at least three capacitors, wherein first terminals of the at least three capacitors are directly connected without magnets to at least three inputs of the individual majority or minority gate, wherein second terminals of the at least three capacitors are directly connected without magnets to a node, and
wherein the at least three capacitors include non-linear polar material; and
an inverter coupled to the inverted sum output of the first 1-bit adder.

### Claim 18 (depends on 17)

The system of claim 17, wherein the first 1-bit adder and the second 1-bit adder include the non-linear polar material.

### Claim 19 (depends on 17)

The system of claim 17, wherein the first 1-bit adder comprises:
a 3-input minority gate to receive a first input, a second input, and a third input; and
a 5-input minority gate to receive the first input, the second input, the third input, and two times an output of the 3-input minority gate, wherein the 3-input minority gate and the 5-input minority gate include the non-linear polar material.

### Claim 20 (depends on 17)

The system of claim 17, wherein the second 1-bit adder comprises:
a 3-input minority gate to receive a fourth input, a fifth input, and a sixth input, wherein the fourth input receives an inverted fourth input, wherein the fifth input receives an inverted fifth input, and wherein the sixth input is the inverted carry output from the first 1-bit adder; and
a 5-input minority gate to receive the fourth input, the fifth input, the sixth input, and two times an output of the 3-input minority gate, wherein the 3-input minority gate and the 5-input minority gate include the non-linear polar material.

### Claim 21 (depends on 15)

The apparatus of claim 15, wherein the 3-input minority gate comprises:
a first capacitor to receive the first input, wherein the first capacitor is directly connected to the node;
a second capacitor to receive the second input, wherein the second capacitor is directly connected to the node; and
a third capacitor to receive the third input, wherein the third capacitor is directly connected to the node, and wherein the first capacitor, the second capacitor, and the third capacitor include the non-linear polar material.