# US 12,118,287 B2 · Automatic generation of sub-cells for an analog integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,118,287 B2 - Document ID: US12118287B2 - Status: Granted - Kind: B2 - Application number: 18/447,916 - Filed: 2023-08-10 - Published: 2024-03-07 - Granted: 2024-10-15 - Earliest claimed: 2021-03-25 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chih-Chiang Chang; Wen-Shen Chou; Yung-Chow Peng; Yung-Hsu Chuang; Yu-Tao Yang; Bindu Madhavi Kasina - Web page: https://patentgrep.com/patent/US12118287B2 ## CPC - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/31: Design entry, e.g. editors specifically adapted for circuit design - G06F 2119/18: Manufacturability analysis or optimisation for manufacturability - Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells. ## Claims ### Claim 1 A method of fabricating an analog integrated circuit, the method comprising: receiving partition information for the analog integrated circuit, wherein the partition information defines types of sub-cells within the analog integrated circuit, each of the types of sub-cells having a corresponding size and functionality and wherein the corresponding size and functionality both vary between the types of sub-cells; determining, based on the partition information, first cut locations along a first direction and second cut locations along a second direction of a non-final layout of the integrated circuit, the first direction and the second direction being orthogonal to each other; partitioning the non-final layout into a plurality of sub-cells based on the first cut locations and the second cut locations; and merging the plurality of sub-cells to produce a layout diagram of the analog integrated circuit. ### Claim 2 (depends on 1) The method of claim 1, further comprising verifying each sub-cell in the plurality of sub-cells prior to merging the sub-cells. ### Claim 3 (depends on 2) The method of claim 2, wherein verifying each sub-cell in the plurality of sub-cells comprises performing design rule checks on each sub-cell in the plurality of sub-cells. ### Claim 4 (depends on 2) The method of claim 2, wherein verifying each sub-cell in the plurality of sub-cells comprises performing a layout versus layout check on each sub-cell in the plurality of sub-cells. ### Claim 5 (depends on 1) The method of claim 1, further comprising verifying the layout diagram of the analog integrated circuit. ### Claim 6 (depends on 1) The method of claim 1, wherein the partition information further includes a starting point and an ending point along the first direction, and a starting point and an ending point along the second direction. ### Claim 7 (depends on 6) The method of claim 6, further comprising verifying each sub-cell in the plurality of sub-cells prior to merging the sub-cells, and including each verified sub-cell in a library. ### Claim 8 (depends on 1) The method of claim 1, further comprising fabricating the analog integrated circuit using the layout diagram. ### Claim 9 A system, comprising: a processing device; and a storage device operably connected to the processing device and storing instructions, that when executed by the processing device, cause operations to be performed, the operations comprising: receiving partition information for an analog integrated circuit, wherein the partition information defines types of sub-cells within the analog integrated circuit, each of the types of sub-cells having a corresponding size and functionality and wherein the corresponding size and functionality both vary between the types of sub-cells; determining, based on the partition information, first cut locations along a first direction and second cut locations along a second direction of a non-final layout of the integrated circuit, the first direction and the second direction being orthogonal to each other; partitioning the non-final layout into a plurality of sub-cells based on the first cut locations and the second cut locations; and merging the plurality of sub-cells to produce a layout diagram of the analog integrated circuit. ### Claim 10 (depends on 9) The system of claim 9, wherein the storage device stores further instructions for verifying each sub-cell in the plurality of sub-cells. ### Claim 11 (depends on 10) The system of claim 10, wherein verifying each sub-cell in the plurality of sub-cells comprises performing design rule checks on each sub-cell in the plurality of sub-cells. ### Claim 12 (depends on 10) The system of claim 10, wherein verifying each sub-cell in the plurality of sub-cells comprises performing a layout versus layout check on each sub-cell in the plurality of sub-cells. ### Claim 13 (depends on 9) The system of claim 9, wherein the storage device stores further instructions for verifying the merged layout diagram of the analog integrated circuit. ### Claim 14 (depends on 9) The system of claim 9, wherein the partition information further includes a starting point and an ending point along the first direction, and a starting point and an ending point along the second direction. ### Claim 15 (depends on 9) The system of claim 9, wherein the storage device stores further instructions for verifying each sub-cell in the plurality of sub-cells, and including verified sub-cells in a library. ### Claim 16 (depends on 9) The system of claim 9, further comprising an input device that transmits the partition information to the processing device. ### Claim 17 (depends on 9) The system of claim 9, wherein the system comprises a computing device. ### Claim 18 A method, comprising: receiving partition information for an analog cell, wherein the partition information defines types of sub-cells within the analog cell, each of the types of sub-cells having a corresponding size and functionality and wherein the corresponding size and functionality both vary between the types of sub-cells; determining, based on the partition information, first cut locations along a first direction and second cut locations along a second direction of a non-final layout of an integrated circuit, the first direction and the second direction being orthogonal to each other; partitioning the non-final layout into a plurality of sub-cells based on the first cut locations and the second cut locations; verifying each sub-cell in the plurality of sub-cells; and producing a layout of the integrated circuit using the plurality of sub-cells. ### Claim 19 (depends on 18) The method of claim 18, wherein: the first cut locations and the second cut locations are determined based on a type of each sub-cell. ### Claim 20 (depends on 18) The method of claim 18, wherein verifying each sub-cell in the plurality of sub-cells comprises at least one of: performing design rule checks on each sub-cell in the plurality of sub-cells; or performing a layout versus layout check on each sub-cell in the plurality of sub-cells.