# US 12,118,286 B2 · Wiring layout design method, program, and recording medium > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,118,286 B2 - Document ID: US12118286B2 - Status: Granted - Kind: B2 - Application number: 17/438,551 - Filed: 2020-03-09 - Published: 2022-05-12 - Granted: 2024-10-15 - Earliest claimed: 2019-03-20 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Yusuke Koumura - Web page: https://patentgrep.com/patent/US12118286B2 ## CPC - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06N 3/006: based on simulated virtual individual or collective life forms, e.g. social simulations or particle swarm optimisation [PSO] - G06F 30/27: using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06N 3/04: Architecture, e.g. interconnection topology - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/048: Activation functions - G06N 3/063: using electronic means - G06N 3/08: Learning methods - G06N 3/092: Reinforcement learning - G06N 7/01: Probabilistic graphical models, e.g. probabilistic networks - G06N 20/00: Machine learning - G06N 3/045: Combinations of networks - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A novel wiring layout design method is provided. A wiring layout in which a starting terminal group and an end terminal group are electrically connected to each other is generated using layout information and a netlist. In the case where the wiring layout satisfies a design rule, a wiring resistance and a parasitic capacitance of the wiring layout are extracted. The layout information is updated using Q learning and a new wiring layout is generated. In the Q learning, a positive reward is given when the values of the wiring resistance and the parasitic capacitance decrease, and a weight of the neural network is updated in accordance with the reward. In the case where the new wiring layout satisfies the design rule, a wiring resistance and a parasitic capacitance of the new wiring layout are extracted. In the case where the change rate of the wiring resistance and the parasitic capacitance is high, the layout information is updated using the Q learning. ## Claims ### Claim 1 A wiring layout design method comprising: a first step of obtaining first layout information, a netlist, and a design rule; a second step of generating a first wiring layout using the first layout information; a third step of obtaining a first parasitic capacitance value that is a parasitic capacitance value of the first wiring layout; a fourth step of generating a second wiring layout using the first layout information; a fifth step of checking whether the second wiring layout satisfies the design rule; a sixth step of obtaining a second parasitic capacitance value that is a parasitic capacitance value of the second wiring layout; a seventh step of performing learning using a result of the fifth step, the first parasitic capacitance value, and the second parasitic capacitance value; and an eighth step of changing the first layout information on the basis of a result of the learning, wherein the first layout information comprises information about an arrangement of terminals, wherein the netlist comprises information about connection relationships between the terminals, and wherein the design rule comprises information about lower limits of at least one of a wiring width, a wiring interval, and a connection diameter. ### Claim 2 (depends on 1) The wiring layout design method according to claim 1, wherein the learning is Q learning. ### Claim 3 (depends on 1) The wiring layout design method according to claim 1, wherein the learning is performed using a neural network. ### Claim 4 (depends on 3) The wiring layout design method according to claim 3, wherein the neural network estimates an action value function. ### Claim 5 A wiring layout design method comprising: a first step of obtaining first layout information; a second step of randomly generating a first wiring layout comprising one of a wiring shape and a wiring path using the first layout information; a third step of obtaining a first parasitic capacitance value that is a parasitic capacitance value of the first wiring layout and a first wiring resistance value that is a wiring resistance value of the first wiring layout; a fourth step of generating a second wiring layout using the first layout information; a fifth step of checking whether the second wiring layout satisfies a design rule; a sixth step of obtaining a second parasitic capacitance value that is a parasitic capacitance value of the second wiring layout and a second wiring resistance value that is a wiring resistance value of the second wiring layout; a seventh step of performing learning using artificial intelligence based on a result of the fifth step, the first parasitic capacitance value, the second parasitic capacitance value, the first wiring resistance value, and the second wiring resistance value; and an eighth step of optimizing parameters of the first layout information on the basis of a result of the learning, wherein the optimized parameters comprise at least one of a wiring length, a wiring width, a distance between a first wiring and a second wiring which is adjacent to the first wiring, and the number of portions where a third wiring overlaps with a fourth wiring. ### Claim 6 (depends on 5) The wiring layout design method according to claim 5, wherein the learning is Q learning. ### Claim 7 (depends on 5) The wiring layout design method according to claim 5, wherein the learning is performed using a neural network. ### Claim 8 (depends on 7) The wiring layout design method according to claim 7 wherein the neural network estimates an action value function.