# US 12,118,285 B1 · Systems and methods for analog integrated circuits (IC) design using quantum evolution algorithms (QEAs)

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- Number: US 12,118,285 B1
- Document ID: US12118285B1
- Status: Granted
- Kind: B1
- Application number: 18/418,454
- Filed: 2024-01-22
- Granted: 2024-10-15
- Earliest claimed: 2024-01-22
- Assignees: Ho Chi Minh City University of Techn
- Applicants: Trang Hoang
- Inventors: Trang Hoang
- Web page: https://patentgrep.com/patent/US12118285B1

## CPC

- G06F 30/36: Circuit design at the analogue level
- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- G06F 30/373: Design optimisation
- G06N 10/00: Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N 10/60: Quantum algorithms, e.g. based on quantum optimisation, quantum Fourier or Hadamard transforms
- G06N 10/80: Quantum programming, e.g. interfaces, languages or software-development kits for creating or handling programs capable of running on quantum computers; Platforms for simulating or accessing quantum computers, e.g. cloud-based quantum computing
- G06F 2111/06: Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

A computer implemented method for designing electrical circuitry is disclosed which comprises: (a) determining types and number of parameters to be optimized and their respective upper boundaries (UB) and lower boundaries (LB) in binary and/or decimal formats for such electrical circuitry using a CAD/CAE/EDA module of a quantum emulator computer; and (b) optimizing the parameters in qubit formats using a quantum evolution optimization module constrained by the upper and lower boundaries; the quantum emulator computer includes the CAD/CAE/EDA program and the quantum evolution optimization module.

## Claims

### Claim 1

A computer implemented method for designing electrical circuitry, comprising:
(a) determining types and number of parameters to be optimized and their respective upper boundaries (UB) and lower boundaries (LB) in either binary or decimal formats for said electrical circuitry using a CAD/CAE/EDA module of a quantum emulator computer; and
(b) optimizing said parameters in qubit formats using a quantum evolution optimization module constrained by said UB and said LB, wherein said quantum emulator computer further comprises said CAD/CAE/EDA module and said quantum evolution optimization module, wherein said step of optimizing said parameters further comprises:
(i) initializing an initial quantum population based on said types and number of said parameters;
(ii) measuring said initial quantum population by collapsing each of said qubits in said quantum population into a binary string (x11, x21, x31 . . . xj,1)1, (x12, x22, x32 . . . xj,2)2, . . . , (x1i, x2i, x3i . . . xj,i)i, . . . , (x1m, x2m, x3m . . . xj,m)m with xj,i∈{0;1}; and
(iii) decoding said binary string by applying a predetermined formula comprising:
value
=
LB
+
decimal
z
j
×
(
UB
-
LB
)
,
wherein a value is a magnitude of each of said parameter to be optimized in a real number domain {R} and a decimal is an unsigned decimal number of said binary string, and wherein j is a total number of bits in said binary string.

### Claim 2 (depends on 1)

The computer implemented method of claim 1 further comprising:
(c) outputting optimal values of said parameters in said binary or decimal formats to said CAD/CAE/EDA module; and
(d) designing and simulating said electrical circuitry using said optimal values.

### Claim 3 (depends on 2)

The computer implemented method of claim 2 wherein
(i)
said step of outputting optimal values of said parameters further comprises using an application interface (API) module configured to automatically transfer said optimal values to said CAD/CAE/EDA module.

### Claim 4 (depends on 3)

The computer implemented method of claim 3 further comprises: receiving said optimal values from said API module, forming a circuit model that fits said parameters and said optimal values, rendering said circuit model to a graphic representation, and simulating and present said circuit model using said CAD/CAE/EDA module.

### Claim 5 (depends on 3)

The computer implemented method of claim 3 wherein said initializing step (i) further comprises:
mapping said parameters to be optimized into said initial quantum population further comprising a plurality of chromosomes and wherein each chromosome further comprises a plurality of genes or said qubits, and wherein each of said qubit is represented by a quantum 0 symbolized as: |0 or a quantum 1 symbolized as: |1; wherein each chromosome is represented by |ψi=Σjci|ψj which is represented by a vector in a form of
❘
"\[LeftBracketingBar]"
ψ
j
〉
↔
(
a
j
β
j
)
.

### Claim 6 (depends on 5)

The computer implemented method of claim 5 wherein said initializing step (i) further comprises: assigning equal probability to each of said chromosome by applying a Hadamard matrix
1
2
⁢
(
1
1
1
-
1
)
to each of said gene in said chromosome and applying a rotation matrix
R
=
(
cos
⁢
(
θ
)
-
sin
⁢
(
θ
)
sin
⁢
(
θ
)
cos
⁢
(
θ
)
)
and wherein an angle ⊖ belongs to an interval
(
0
;
π
2
]
.

### Claim 7 (depends on 1)

The computer implemented method of claim 1 wherein said measuring said initial quantum population further comprises applying a formula
{
p
⁡
(
α
)
≤
❘
"\[LeftBracketingBar]"
α
j
,
i
2
❘
"\[RightBracketingBar]"
→
x
j
,
i
=
0
p
⁡
(
α
)
>
❘
"\[LeftBracketingBar]"
α
j
,
i
2
❘
"\[RightBracketingBar]"
→
x
j
,
i
=
1
.

### Claim 8 (depends on 1)

The computer implemented method of claim 1 further comprising determining an objective function (fobj) for said quantum population by applying said parameters to be optimized to calculate a product of power consumption and time delay in said electrical circuitry.

### Claim 9 (depends on 1)

The computer implemented method of claim 1 further comprising determining an objective function (fobj) for said quantum population by applying said parameters to be optimized to calculate a product of bandwidth and gain of said electrical circuitry.

### Claim 10 (depends on 1)

The computer implemented method of claim 1 further comprising generating a new quantum population by rotating said initial quantum population to an optimal angle using a rotation matrix
R
=
(
cos
⁡
(
θ
)
-
sin
⁡
(
θ
)
sin
⁡
(
θ
)
cos
⁢
(
θ
)
)
.

### Claim 11 (depends on 10)

The computer implemented method of claim 10 further comprising determining and selecting said chromosomes that need further a rotation δ⊖ angle to said optimal angle to update said quantum population.

### Claim 12 (depends on 11)

The computer implemented method of claim 11 further comprising outputting said chromosomes whose rotation angle is 0 in said decimal format to said CAD/CAE/EDA module.

### Claim 13 (depends on 1)

The computer implemented method of claim 1 further comprising mutating said quantum population by applying a quantum Pauli gate
X
=
(
0
1
1
0
)
to a jth chromosome using a formula
(
α
j
,
i
′
β
j
,
i
′
)
=
(
0
1
1
0
)
⁢
(
α
j
,
i
β
j
,
i
)
.

### Claim 14

A computer system for designing and simulating an electrical circuitry, comprising:
a CAD/CAE/EDA module operable to assisting in a design and a simulation of said electrical circuitry; and
a quantum emulator module, electrically coupled to said CAD/CAE/EDA module, operable, to perform the following steps:
(a) determining types and number of parameters to be optimized and their respective upper boundaries (UB) and lower boundaries (LB) in either binary or decimal formats for said electrical circuitry using said CAD/CAE/EDA module; and
(b) optimizing said parameters in qubit formats using a quantum evolution optimization module constrained by said UB and said LB, wherein said quantum emulator module further comprises said quantum evolution optimization module, wherein said optimizing said parameters further comprises:
(j) initializing an initial quantum population based on said types and number of said parameters;
measuring said initial quantum population by collapsing each of said qubits in said quantum population into a binary string (x11, x21, x31 . . . xj,1)1, (x12, x22, x32 . . . xj,2)2, . . . , (x1i, x2i, x3i . . . xj,i)i, . . . , (x1m, x2m, x3m . . . xj,m)m with xj,i∈{0; 1}; and
decoding said binary string by applying a predetermined formula to said binary string, said predetermined formula is defined as
value
=
LB
+
decimal
2
j
×
(
UB
-
LB
)
,
wherein a value is a magnitude of each of said parameter to be optimized in a real number domain {R} and a decimal is an unsigned decimal number of said binary string, and wherein j is a total number of bits in said binary string.

### Claim 15 (depends on 14)

The computer system of claim 14 wherein said quantum emulator module further comprises:
a quantum random access memory (Q-RAM) for storing said parameters in qubit formats; and
a quantum circuit (Q-circuits) for performing quantum gate calculations including quantum inversion, quantum mutation, and quantum rotation.

### Claim 16 (depends on 15)

The computer system of claim 15 wherein said quantum emulator module further comprises a software library for storing quantum emulator software programs.

### Claim 17 (depends on 16)

The computer system of claim 16 wherein said CAD/CAE/EDA module further comprises circuitry models for different design applications.

### Claim 18 (depends on 17)

The computer system of claim 17 further comprises an application interface (API) module configured to automatically transfer said optimal values to said CAD/CAE/EDA module.

### Claim 19 (depends on 18)

The computer system of claim 18 wherein said algorithm further comprises:
outputting optimal values of said parameters in said binary or decimal formats to said CAD/CAE/EDA module; and
designing and simulating said electrical circuitry using said optimal values.

### Claim 20 (depends on 19)

The computer system of claim 19 wherein said CAD/CAE/EDA module further comprises:
registers operable to receive said optimal values from said API module;
a geometric modeling module and an engineering analysis model operable to form a circuit model that fits said parameters and said optimal values;
a CAD graphic module operable to render said circuit model to a graphic representation;
a design review and valuation module operable to simulate present said circuit model.