# US 12,118,248 B2 · Managed NAND data compression

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- Number: US 12,118,248 B2
- Document ID: US12118248B2
- Status: Granted
- Kind: B2
- Application number: 18/206,934
- Filed: 2023-06-07
- Published: 2024-04-11
- Granted: 2024-10-15
- Earliest claimed: 2017-06-19
- Applicants: Lodestar Licensing Group, LLC
- Inventors: Sebastien Andre Jean
- Web page: https://patentgrep.com/patent/US12118248B2

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0608: {Saving storage space on storage systems}
- G06F 3/0611: {in relation to response time}
- G06F 3/064: {Management of blocks}
- G06F 3/0647: {Migration mechanisms}
- G06F 3/0649: {Lifecycle management}
- G06F 3/0661: {Format or protocol conversion arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/068: {Hybrid storage device}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

## Claims

### Claim 1

A system comprising:
a plurality of non-volatile memory cells; and
a memory controller configured to:
provide, to a host processor, an indication of available data operations that the memory controller is configured to perform on the plurality of non-volatile memory cells;
receive, from the host processor, an indication of a data operation of the available data operations; and
perform the data operation on the plurality of non-volatile memory cells.

### Claim 2 (depends on 1)

The system of claim 1, wherein the host processor is disposed on a separate chip than the memory controller and the plurality of non-volatile memory cells.

### Claim 3 (depends on 1)

The system of claim 1, wherein the data operation corresponds to a garbage collection.

### Claim 4 (depends on 1)

The system of claim 1, wherein the data operation corresponds to maintaining contiguous blocks of data stored on the plurality of non-volatile memory cells.

### Claim 5 (depends on 1)

The system of claim 1, wherein the host processor is configured to assign identified data operations to the memory controller to reduce bus traffic delays between the host processor and the system.

### Claim 6 (depends on 1)

The system of claim 1, wherein the available data operations comprise read, write, and erase operations.

### Claim 7 (depends on 1)

The system of claim 1, wherein the plurality of non-volatile memory cells comprises a three-dimensional architecture semiconductor memory array.

### Claim 8 (depends on 1)

The system of claim 1, wherein the memory controller is configured to perform the data operation on the plurality of non-volatile memory cells based on determining that one or more access operations to the plurality of non-volatile memory cells are completed.

### Claim 9 (depends on 1)

The system of claim 1, wherein the memory controller is configured to perform the data operation on the plurality of non-volatile memory cells during a detected period of inactivity associated with the plurality of non-volatile memory cells.

### Claim 10

A method, comprising:
providing, via a memory controller configured to couple to a plurality of non-volatile memory cells, an indication to a host processor, wherein the indication corresponds to available data operations that the memory controller is configured to perform on the plurality of non-volatile memory cells;
receiving, via the memory controller, an indication of a data operation selected by the host processor from the available data operations; and
performing, via the memory controller, the data operation on the plurality of non-volatile memory cells.

### Claim 11 (depends on 10)

The method of claim 10, comprising performing, via the memory controller, the data operation on the plurality of non-volatile memory cells during a detected period of inactivity associated with the plurality of non-volatile memory cells.

### Claim 12 (depends on 10)

The method of claim 10, comprising performing, via the memory controller, the data operation on the plurality of non-volatile memory cells based on determining that one or more access operations to the plurality of non-volatile memory cells are completed.

### Claim 13 (depends on 10)

The method of claim 10, wherein the data operation comprises maintaining, via the memory controller, contiguous blocks of data stored on the plurality of non-volatile memory cells.

### Claim 14 (depends on 10)

The method of claim 10, wherein performing, via the memory controller, the data operation comprises performing a garbage collection on the plurality of non-volatile memory cells based on the indication that the one or more contiguous portions of data are no longer used by the host processor.

### Claim 15

A tangible, non-transitory, computer-readable medium comprising instructions that, when executed by a memory controller communicatively coupled to a plurality of non-volatile memory cells, causes a storage system to perform operations comprising:
receiving, from a host processor, an instruction configured to identify a data operation and a subset of non-volatile memory cells of the plurality of non-volatile memory cells, wherein the data operation corresponds to a selected data operation from a plurality of data operations that the memory controller is configured to perform on the plurality of non-volatile memory cells; and
performing the data operation on the subset of non-volatile memory cells during a detected period of inactivity associated with the subset of non-volatile memory cells.

### Claim 16 (depends on 15)

The tangible, non-transitory, computer-readable medium of claim 15, wherein the operations comprise performing the data operation during the detected period of read and write inactivity corresponding to the plurality of non-volatile memory cells.

### Claim 17 (depends on 15)

The tangible, non-transitory, computer-readable medium of claim 15, wherein the operations comprise performing the data operation on the plurality of non-volatile memory cells based on determining that one or more access operations to the plurality of non-volatile memory cells are completed.

### Claim 18 (depends on 15)

The tangible, non-transitory, computer-readable medium of claim 15, wherein the operations comprises maintaining contiguous blocks of data stored on the plurality of non-volatile memory cells.

### Claim 19 (depends on 15)

The tangible, non-transitory, computer-readable medium of claim 15, wherein the data operation corresponds to a garbage collection.

### Claim 20 (depends on 19)

The tangible, non-transitory, computer-readable medium of claim 19, wherein the operations comprise receiving an indication that the subset of non-volatile memory cells are ready for garage collection based on receiving the instruction.