# US 12,118,241 B2 · Memory controller, memory system, and operating method thereof

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- Number: US 12,118,241 B2
- Document ID: US12118241B2
- Status: Granted
- Kind: B2
- Application number: 17/233,210
- Filed: 2021-04-16
- Published: 2021-07-29
- Granted: 2024-10-15
- Earliest claimed: 2017-10-27
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Do Hun Kim
- Web page: https://patentgrep.com/patent/US12118241B2

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 11/1064: {in cache or content addressable memories}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0611: {in relation to response time}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/068: {Hybrid storage device}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0866: for peripheral storage systems, e.g. disk cache
- G06F 12/10: Address translation
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/608: Details relating to cache mapping
- G06F 2212/657: Virtual address space management
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 2029/0411: {Online error correction}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory controller includes a cache memory, a host control circuit, and a flash translation layer. The host control circuit receives a read command and a logical address from a host, reads out mapping information corresponding to the logical address from a buffer memory device, and caches the mapping information in the cache memory. The flash translation layer reads a physical address corresponding to the logical address from the mapping information cached in the cache memory.

## Claims

### Claim 1

A memory controller, comprising:
a cache memory;
a buffer memory device storing logical-physical address mapping information loaded from a nonvolatile memory device;
a host control circuit configured to receive a read command and a logical address from a host, issue a first command, in response to the read command, to read out mapping information corresponding to the logical address, from the buffer memory device when the mapping information corresponding to the logical address is cache-missed in the cache memory, and cache the mapping information from the buffer memory device in the cache memory; and
a flash translation layer configured to receive the logical address from the host control circuit, and issue a second command to read a physical address corresponding to the logical address from the mapping information cached in the cache memory.

### Claim 2 (depends on 1)

The memory controller of claim 1, further comprising:
a flash control circuit configured to read data corresponding to the read command from the nonvolatile memory device based on the physical address.

### Claim 3 (depends on 1)

The memory controller of claim 1, further comprising an error correction circuit coupled between the buffer memory device and the cache memory,
wherein the error correction circuit is configured to perform an ECC decoding operation on the mapping information output from the buffer memory device and to generate ECC decoded mapping information, and
wherein the cache memory caches the ECC-decoded mapping information.

### Claim 4 (depends on 2)

The memory controller of claim 2, wherein the buffer memory device is configured to buffer the data read from the nonvolatile memory device.

### Claim 5 (depends on 2)

The memory controller of claim 2, wherein when the host control circuit receives a write command, a write logical address, and write data from the host, the flash translation layer maps a write physical address to the write logical address, and updates mapping information stored in the buffer memory device with the write physical address mapped to the write logical address, and the flash control circuit programs the write data in the nonvolatile memory device based on the write physical address.

### Claim 6 (depends on 5)

The memory controller of claim 5, wherein the flash translation layer updates the mapping information stored in the buffer memory device by reading chunk data corresponding to the write logical address from the buffer memory device, modifying section data corresponding to the write physical address that is included in the chunk data, and writing modified chunk data including the modified section data to the buffer memory device.

### Claim 7

A method of operating a memory system, the method comprising:
receiving, by a host control circuit, a read command and a logical address from a host;
searching a cache memory for mapping information corresponding to the logical address;
issuing a first command, in response to the read command, by the host control circuit when the mapping information corresponding to the logical address is cache-missed in the cache memory;
reading the mapping information corresponding to the logical address, from a buffer memory device storing logical-physical address mapping information loaded from a nonvolatile memory device;
caching the mapping information from the buffer memory device in the cache memory, in response to the first command, by the host control circuit;
transferring the logical address from the host control circuit to a flash translation layer;
issuing a second command, by the flash translation layer; and
reading, by the flash translation layer, a physical address corresponding to the logical address from the mapping information cached in the cache memory, in response to the second command.

### Claim 8 (depends on 7)

The method of claim 7, wherein the caching comprises:
executing an ECC decoding operation on the mapping information to generate ECC decoded mapping information; and
caching the ECC-decoded mapping information in the cache memory.

### Claim 9 (depends on 7)

The method of claim 7, further comprising:
receiving a write command, a write logical address, and write data from the host;
mapping a write physical address to the write logical address;
updating mapping information stored in the buffer memory device with the write physical address; and
programming the write data in the nonvolatile memory device based on the write physical address.

### Claim 10 (depends on 9)

The method of claim 9, wherein updating the mapping information comprises:
reading chunk data corresponding to the write logical address from the buffer memory device;
modifying section data corresponding to the write physical address that is included in the chunk data; and
writing modified chunk data including the modified section data to the buffer memory device.

### Claim 11

A memory system, comprising:
a nonvolatile memory device;
a buffer memory device configured to store logical-physical address mapping information loaded from the nonvolatile memory device; and
a memory controller configured to control operations of the nonvolatile memory device and the buffer memory device,
wherein the memory controller comprises:
a cache memory;
a host control circuit configured to receive a read command and a logical address from a host, issue a first command, in response to the read command, to read out mapping information corresponding to the logical address from the buffer memory device when the mapping information corresponding to the logical address is cache-missed in the cache memory, and cache the mapping information from the buffer memory device in the cache memory; and
a flash translation layer configured to receive the logical address from the host control circuit, and issue a second command to read a physical address corresponding to the logical address from the mapping information cached in the cache memory.

### Claim 12 (depends on 11)

The memory system of claim 11, wherein the memory controller further comprises a flash control circuit configured to read data corresponding to the read command from the nonvolatile memory device based on the physical address.

### Claim 13 (depends on 11)

The memory system of claim 11, wherein the memory controller further comprises an error correction circuit coupled between the buffer memory device and the cache memory,
wherein the error correction circuit is configured to perform an ECC decoding operation on the mapping information output from the buffer memory device and to generate ECC decoded mapping information, and
wherein the cache memory caches the ECC-decoded mapping information.

### Claim 14 (depends on 12)

The memory system of claim 12, wherein the buffer memory device is configured to buffer the data read from the nonvolatile memory device.

### Claim 15 (depends on 12)

The memory system of claim 12, wherein when the host control circuit receives a write command, a write logical address, and write data from the host, the flash translation layer maps a write physical address to the write logical address, and updates the logical-physical address mapping information stored in the buffer memory device with the write physical address mapped to the write logical address, and the flash control circuit programs the write data in the nonvolatile memory device based on the write physical address.

### Claim 16 (depends on 15)

The memory system of claim 15, wherein the flash translation layer updates the logical-physical address mapping information stored in the buffer memory device by reading chunk data corresponding to the write logical address from the buffer memory device, modifying section data corresponding to the write physical address that is included in the chunk data, and writing modified chunk data including the modified section data to the buffer memory device.