# US 12,118,236 B2 · Dynamically allocating memory controller resources for extended prefetching

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- Number: US 12,118,236 B2
- Document ID: US12118236B2
- Status: Granted
- Kind: B2
- Application number: 17/446,318
- Filed: 2021-08-30
- Published: 2023-03-02
- Granted: 2024-10-15
- Earliest claimed: 2021-08-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Eric E. Retter; Lilith Hale; Brad William Michael; John Dodson
- Web page: https://patentgrep.com/patent/US12118236B2

## CPC

- G06F 3/0656: {Data buffering arrangements}
- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0631: {by allocating resources to storage systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory controller comprises a system bus interface that connects the MC to a system processor, a system memory interface that connects the MC to a system memory, a read buffer comprising a plurality of entries constituting storage areas, the entries comprising at least one read buffer entry (RBE) and at least one extended prefetch read buffer entry (EPRBE), read buffer logic, dynamic controls that are used by the read buffer logic, and an MC processor comprising at least one extended prefetch machine (EPM), each corresponding to one of the at least EPRBEs, where the MC processor is configured to allocate and deallocate EPRBEs and RBEs according to an allocation method using the dynamic controls.

## Claims

### Claim 1

A memory controller (MC) comprising:
a read buffer comprising a plurality of entries constituting storage areas, the entries comprising at least one read buffer entry (RBE) and at least one extended prefetch read buffer entry (EPRBE);
read buffer logic that is configured to:
determine a buffer ratio;
conditioned upon the buffer ratio exceeding a ratio threshold, increase a number of EPRBEs without exceeding a high dynamic extended prefetch read machine limit; and
conditioned upon the buffer ratio falling below the ratio threshold, decrease the number of EPRBEs without falling below a low dynamic extended prefetch read machine limit; and
an MC processor comprising:
at least one extended prefetch machine (EPM) corresponding to the at least one EPRBE;
wherein:
the MC processor is configured to allocate and deallocate EPRBEs and RBEs.

### Claim 2 (depends on 1)

The memory controller of claim 1, wherein the
buffer ratio is: (a) a number of EPMs hit by prefetch requests divided by (b) a number of EPMs dispatched, within a programmable window.

### Claim 3 (depends on 2)

The memory controller of claim 2, wherein the increasing of the number of EPRBEs and the decreasing of the number of EPRBEs is an increase of one for the programmable window.

### Claim 4 (depends on 2)

The memory controller of claim 2, wherein the increasing of the number of EPRBEs and the decreasing of the number of EPRBEs is an increase according to an equation that uses rate control information to define rate control.

### Claim 5 (depends on 2)

The memory controller of claim 2, further comprising dynamic controls that are used by the read buffer logic, and wherein:
the high dynamic extended prefetch read machine limit is stored in the dynamic controls; and
the low dynamic extended prefetch read machine limit is stored in the dynamic controls.

### Claim 6 (depends on 1)

The memory controller of claim 1, wherein the memory controller initializes with the low dynamic extended prefetch read machine limit number of EPRBEs.

### Claim 7 (depends on 1)

The memory controller of claim 1, wherein the read buffer logic is configured to:
determine a number of prefetch reads within a programmable window;
conditioned upon the number of reads being greater than a reads threshold, the number of EPRBEs is increased; and
conditioned upon the number of reads being less than the reads threshold, the number of EPRBEs is decreased.

### Claim 8 (depends on 1)

The memory controller of claim 1, wherein the read buffer logic is further configured to, conditioned upon a determination that a number of existing EPRBEs is greater than or equal to a stop threshold, send a signal to the MC processor to prohibit the creation of new EPRBEs.

### Claim 9

A method for operating a memory controller (MC) comprising:
receiving, by the memory controller via a system bus interface, a prefetch request from a system processor;
responsive to the prefetch request, allocating and deallocating, by an MC processor, read buffer entries (RBEs) and extended prefetch read buffer entries (EPRBEs) by, conditioned upon a determination that a number of currently allocated EPRBEs exceeds a drop threshold, sending a signal to the MC processor to actively reduce a number of EPRBEs, and wherein the number of EPRBEs for active reduction are determined to satisfy candidate criteria by being in a state in which data the number of EPRBEs contain has been fetched from a system memory, but have not been hit by a read request;
wherein:
the RBEs and the EPRBEs are contained within a read buffer of the MC; and
the MC processor comprises extended prefetch machines (EPMs) corresponding to the at least one EPRBE.

### Claim 10 (depends on 9)

The method of claim 9, wherein the allocating and deallocating further comprises:
determining a buffer ratio as: (a) a number of EPMs hit by prefetch requests divided by (b) a number of EPMs dispatched, within a programmable window;
conditioned upon the buffer ratio exceeding a ratio threshold, increasing the number of EPRBEs; and
conditioned upon the buffer ratio falling below the ratio threshold, decreasing the number of EPRBEs.

### Claim 11 (depends on 9)

The method of claim 9, wherein the allocating and deallocating further comprises:
determining a number of prefetch reads within a programmable window;
conditioned upon the number of reads being greater than a reads threshold, increasing the number of EPRBEs; and
conditioned upon the number of reads being less than the reads threshold, decreasing the number of EPRBEs.

### Claim 12 (depends on 9)

The method of claim 9, wherein the allocating and deallocating further comprises, conditioned upon determining that a number of existing EPRBEs is greater than or equal to a stop threshold, sending a signal to the MC processor to prohibit the creation of new EPRBEs.

### Claim 13 (depends on 9)

The method of claim 9, wherein
the MC processor actively reduces the number of EPRBEs by dropping one EPRBE in response to the signal.

### Claim 14

A memory controller (MC) comprising:
a system memory interface that connects the MC to a system memory;
a read buffer comprising a plurality of entries constituting storage areas, the entries comprising at least one read buffer entry (RBE) and at least one extended prefetch read buffer entry (EPRBE);
read buffer logic that is configured to:
conditioned upon a determination that a number of currently allocated EPRBEs exceeds a drop threshold, send a signal to an MC processor to actively reduce a number of EPRBEs, wherein the number of EPRBEs for active reduction are determined to satisfy candidate criteria by being in a state in which data the number of EPRBEs contain has been fetched from the system memory, but have not been hit by a read request; and
the MC processor comprising:
at least one extended prefetch machine (EPM) corresponding to the at least one EPRBE;
wherein:
the MC processor is configured to allocate and deallocate EPRBEs and RBEs.

### Claim 15 (depends on 14)

The memory controller of claim 14, wherein the MC processor actively reduces the number of EPRBEs by dropping one EPRBE in response to the signal.

### Claim 16 (depends on 15)

The memory controller of claim 15, wherein the one EPRBE dropped is a first EPRBE determined to meet the candidate criteria.

### Claim 17 (depends on 16)

The memory controller of claim 16, wherein the MC processor utilizes an excessive drop counter to prevent excessive drops from occurring.

### Claim 18 (depends on 13)

The method of claim 13, wherein the one EPRBE dropped is a first EPRBE determined to meet the candidate criteria.

### Claim 19 (depends on 18)

The method of claim 18, wherein the MC processor utilizes an excessive drop counter to prevent excessive drops from occurring.