# US 12,118,235 B2 · Method and system for buffer allocation management for a memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,118,235 B2 - Document ID: US12118235B2 - Status: Granted - Kind: B2 - Application number: 17/402,192 - Filed: 2021-08-13 - Published: 2023-02-16 - Granted: 2024-10-15 - Earliest claimed: 2021-08-13 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Paul Hanham; Julien Margetts; Matthew Stephens - Web page: https://patentgrep.com/patent/US12118235B2 ## CPC - G06F 3/0656: {Data buffering arrangements} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/061: {Improving I/O performance} - G06F 3/0631: {by allocating resources to storage systems} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block. ## Claims ### Claim 1 A non-transitory processor-readable media comprising processor-readable instructions, such that, when executed by a processor, causes the processor to: identify a request to access a memory device, the memory device having an associated buffer memory; in response to the request, determine whether a request count associated with a buffer memory block in the buffer memory satisfies a reference threshold, wherein the reference threshold corresponds to a maximum storage size of the buffer memory block; update, in accordance with a determination that the request count does not satisfy the reference threshold, the request count by incrementing a reference counter associated with the buffer memory block; allocate an overflow counter to the reference counter, in response to a determination that the request count satisfies the reference threshold; increment, in response to a determination that the overflow counter is allocated to the reference counter, an overflow count associated with the overflow counter. ### Claim 2 (depends on 1) The non-transitory processor-readable media of claim 1, wherein the processor is further caused to: generate at least one memory address corresponding respectively to at least one command block, the at least one command block being associated with a command to the memory device from which the request to access the memory device is identified; and allocate the at least one memory address to a buffer addressing unit associated with a host interface, the at least one memory address including a buffer memory identifier associated with the buffer memory block and a buffer memory address associated with the buffer memory block. ### Claim 3 (depends on 2) The non-transitory processor-readable media of claim 2, wherein the processor is further caused to: divide the command into a plurality of the at least one command blocks, in response to a determination that the command exceeds a reference threshold associated with the buffer memory block; and generate a linked list comprising the plurality of command blocks, in response to the determination that the command exceeds a buffer threshold. ### Claim 4 (depends on 3) The non-transitory processor-readable media of claim 3, wherein the processor is further caused to: associate at least a first command block of the plurality of command blocks with a second command block of the plurality of command blocks, and append a next memory address associated with the second command block to the first command block, to generate the linked list comprising the plurality of command blocks. ### Claim 5 (depends on 3) The non-transitory processor-readable media of claim 3, wherein the processor is further caused to: associate at least a first command block of the plurality of command blocks with a second command block of the plurality of command blocks, to generate the linked list comprising the plurality of command blocks. ### Claim 6 (depends on 2) The non-transitory processor-readable media of claim 2, wherein the processor is further caused to: write the at least one command block to the buffer memory address of the buffer memory block. ### Claim 7 (depends on 6) The non-transitory processor-readable media of claim 6, wherein the processor is further caused to: determine whether the command exceeds the buffer threshold. ### Claim 8 (depends on 6) The non-transitory processor-readable media of claim 6, wherein the host interface includes the buffer addressing unit. ### Claim 9 (depends on 6) The non-transitory processor-readable media of claim 6, wherein the buffer memory block comprises SRAM. ### Claim 10 A non-transitory processor-readable media comprising processor-readable instructions, such that, when executed by a processor, causes the processor to: identify a request to access a memory device, the memory array having an associated buffer memory; in response to the request, send a completion notification to a buffer manager accelerator, the completion notification indicating at least one command block address corresponding to at least one command block at a buffer memory block in the buffer memory, wherein a reference counter is associated with the buffer memory block; decrement, in response to a determination that an overflow counter is allocated to the reference counter, the overflow counter; determine whether a request count satisfies a reference threshold associated with the reference counter, wherein the reference threshold corresponds to a maximum storage size of the buffer memory block; and deallocate the overflow counter from the reference counter, in response to a determination that the request count satisfies the reference threshold. ### Claim 11 (depends on 10) The non-transitory processor-readable media of claim 10, wherein the processor is further caused to: determine whether the request count indicates that at least one request is associated with the at least one command block; deallocate the at least one command block address corresponding to the at least one command block, in response to a determination that the request count indicates that no request is associated with the at least one command block; and send the completion notification to the buffer manager accelerator in response to the processor being caused to execute a command to the memory array from which the request to access the memory array is identified. ### Claim 12 (depends on 11) The non-transitory processor-readable media of claim 11, wherein the command is associated with the at least one command block. ### Claim 13 (depends on 11) The non-transitory processor-readable media of claim 11, wherein the processor is further caused to: reconstruct the command from the at least one command block. ### Claim 14 (depends on 10) The non-transitory processor-readable media of claim 10, wherein the processor is further caused to: reconstruct the command from a plurality of the at least one command blocks. ### Claim 15 (depends on 14) The non-transitory processor-readable media of claim 14, wherein the processor is further caused to: determine whether the at least one command block indicates a next command block address associated with a next command block; and obtain the next command block from a next buffer memory block. ### Claim 16 (depends on 14) The non-transitory processor-readable media of claim 14, wherein the at least one command block and the next command block comprise a linked list. ### Claim 17 (depends on 10) The non-transitory processor-readable media of claim 10, wherein the processor is further caused to: obtain the at least one command block from the buffer memory block. ### Claim 18 A storage device, comprising: a non-volatile memory; a host interface configured to: generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device; allocate the at least one memory address to a buffer addressing unit associated with a host interface, the at least one memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block; determine whether a request count associated with the buffer memory block satisfies a reference threshold; update, in accordance with a determination that the request count does not satisfy the reference threshold, the request count by incrementing a reference counter associated with the buffer memory block; allocate an overflow counter to the reference counter, in response to a determination that the request count satisfies the reference threshold; increment, in response to a determination that the overflow counter is allocated to the reference counter, an overflow count associated with the overflow counter; and decrement, in response to a determination that the overflow counter is allocated to the reference counter, the overflow count associated with the overflow counter; a flash interface configured to: reconstruct the command from the command block; and send the completion notification to the host interface, the completion notification indicating the command block address corresponding to the command block at the buffer memory block. ### Claim 19 (depends on 18) The storage device of claim 18, wherein the processor is further caused to: reconstruct the command from a plurality of command blocks, wherein the at least one command block comprises the plurality of command blocks. ### Claim 20 (depends on 19) The storage device of claim 19, wherein the processor is further caused to: determine whether the command block indicates a next command block address associated with a next command block; and obtain the next command block from a next buffer memory block, wherein the command block and the next command block comprise a linked list.