# US 12,118,220 B2 · Elastic persistent memory regions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,118,220 B2 - Document ID: US12118220B2 - Status: Granted - Kind: B2 - Application number: 18/200,685 - Filed: 2023-05-23 - Published: 2023-09-21 - Granted: 2024-10-15 - Earliest claimed: 2021-04-16 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Joseph H. Steinmetz; Luca Bert; William Akin - Web page: https://patentgrep.com/patent/US12118220B2 ## CPC - G06F 3/0631: {by allocating resources to storage systems} - G06F 12/0873: Mapping of cache memory to specific storage devices or parts thereof - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0644: {Management of space entities, e.g. partitions, extents, pools} - G06F 3/068: {Hybrid storage device} - G06F 12/0808: with cache invalidating means (G06F12/0815 takes precedence) - G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems - G06F 2212/1021: Hit rate improvement - G06F 2212/1024: Latency reduction - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F 2212/1044: Space efficiency improvement - G06F 2212/214: Solid state disk - G06F 2212/261: Storage comprising a plurality of storage devices - G06F 2212/312: In storage controller - G06F 2212/502: using adaptive policy - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system includes a memory and at least one processing device, operatively coupled to the memory, to perform operations including causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device. The PMR utilizes a power protection mechanism to prevent data loss in an event of power loss. ## Claims ### Claim 1 A system comprising: a memory; and at least one processing device, operatively coupled to the memory, to perform operations comprising: causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device, wherein the PMR utilizes a power protection mechanism to prevent data loss in an event of power loss; and managing PMR caching with respect to the PMR by using a caching mechanism that manages page eviction based on a set of key registers. ### Claim 2 (depends on 1) The system of claim 1, wherein the operations further comprise writing data from the volatile memory device to the non-volatile memory device in the event of power loss. ### Claim 3 (depends on 1) The system of claim 1, wherein the volatile memory device includes a Double Data Rate (DDR) device. ### Claim 4 (depends on 1) The system of claim 1, a wherein the set of key registers is internal to a controller. ### Claim 5 (depends on 1) The system of claim 1, wherein the set of key registers comprises at least one: a key register indicating a size of the PMR, a key register indicating a size of each page of the PMR, a key register indicating a number of pages of the PMR, or a key register controlling restoration and eviction of PMR data. ### Claim 6 (depends on 1) The system of claim 1, wherein the operations further comprise: receiving a PMR access request to perform a data operation; and performing the data operation using the caching mechanism. ### Claim 7 (depends on 1) The system of claim 1, wherein the operations further comprise managing at least one of shutdown or startup using the caching mechanism. ### Claim 8 A method comprising: causing, by a processing device, a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device, wherein the PMR utilizes a power protection mechanism to prevent data loss in an event of power loss; and managing, by the processing device, PMR caching with respect to the PMR by using a caching mechanism that manages page eviction based on a set of key registers. ### Claim 9 (depends on 8) The method of claim 8, further comprising writing, by the processing device, data from the volatile memory device to the non-volatile memory device in the event of power loss. ### Claim 10 (depends on 8) The method of claim 8, wherein the volatile memory device includes a Double Data Rate (DDR) device. ### Claim 11 (depends on 8) The method of claim 8, wherein the set of key registers comprises at least one: a key register indicating a size of the PMR, a key register indicating a size of each page of the PMR, a key register indicating a number of pages of the PMR, or a key register controlling restoration and eviction of PMR data. ### Claim 12 (depends on 8) The method of claim 8, further comprising: receiving, by the processing device, a PMR access request to perform a data operation; and performing, by the processing device, the data operation using the caching mechanism. ### Claim 13 (depends on 8) The method of claim 8, further comprising managing, by the processing device using the caching mechanism, at least one of shutdown or startup. ### Claim 14 A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device, wherein the PMR utilizes a power protection mechanism to prevent data loss in an event of power loss; and managing, by the processing device, PMR caching with respect to the PMR by using a caching mechanism that manages page eviction based on a set of key registers. ### Claim 15 (depends on 14) The non-transitory computer-readable storage medium of claim 14, wherein the operations further comprise writing data from the volatile memory device to the non-volatile memory device in the event of power loss. ### Claim 16 (depends on 14) The non-transitory computer-readable storage medium of claim 14, wherein the set of key registers comprises at least one: a key register indicating a size of the PMR, a key register indicating a size of each page of the PMR, a key register indicating a number of pages of the PMR, or a key register controlling restoration and eviction of PMR data. ### Claim 17 (depends on 14) The non-transitory computer-readable storage medium of claim 14, wherein the operations further comprise: receiving a PMR access request to perform a data operation; and performing the data operation using the caching mechanism. ### Claim 18 (depends on 14) The non-transitory computer-readable storage medium of claim 14, wherein the operations further comprise managing at least one of shutdown or startup using the caching mechanism.