# US 12,118,130 B2 · Circuitry and methods for low-latency efficient chained decryption and decompression acceleration > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,118,130 B2 - Document ID: US12118130B2 - Status: Granted - Kind: B2 - Application number: 17/214,820 - Filed: 2021-03-27 - Published: 2022-09-29 - Granted: 2024-10-15 - Earliest claimed: 2021-03-27 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Vinodh Gopal - Web page: https://patentgrep.com/patent/US12118130B2 ## CPC - G06F 21/72: in cryptographic circuits - G06F 21/64: Protecting data integrity, e.g. using checksums, certificates or signatures - H04L 9/0637: {Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]} - H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC} - H04L 2209/72: Signcrypting, i.e. digital signing and encrypting simultaneously - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Systems, methods, and apparatuses for low-latency page efficient chained decryption and decompression acceleration are described. In one embodiment, a processor comprises a hardware processor core, and an accelerator circuit coupled to the hardware processor core, the accelerator circuit to: in response to a descriptor, comprising an indication of a hash key and encrypted data to be decrypted, from the hardware processor core, perform a determination that the encrypted data is to be read in an encrypted order or a reverse order from the encrypted order, in response to the determination that the encrypted data is to be read in the reverse order, generate a resultant authentication tag in the reverse order for the encrypted data based at least in part on the hash key without reordering the encrypted data in the reverse order into the encrypted order, and, in response to the determination that the encrypted data is to be read in the encrypted order, generate the resultant authentication tag in the encrypted order for the encrypted data based at least in part on the hash key. ## Claims ### Claim 1 An apparatus comprising: a hardware processor core; and an accelerator circuit coupled to the hardware processor core, the accelerator circuit to: in response to a descriptor, comprising an indication of a hash key and encrypted data to be decrypted, from the hardware processor core, perform a determination that the encrypted data is to be read in an encrypted order or a reverse order from the encrypted order, in response to the determination that the encrypted data is to be read in the reverse order, generate a resultant authentication tag in the reverse order for the encrypted data based at least in part on the hash key without reordering the encrypted data in the reverse order into the encrypted order, and, in response to the determination that the encrypted data is to be read in the encrypted order, generate the resultant authentication tag in the encrypted order for the encrypted data based at least in part on the hash key. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the accelerator circuit is to, in response to the descriptor, generate a first authentication tag in the encrypted order for a first plurality of cipher blocks of the encrypted data, generate a second authentication tag in the reverse order for a second plurality of cipher blocks of the encrypted data, and combine the first authentication tag and the second authentication tag into the resultant authentication tag. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the accelerator circuit is to, in response to the descriptor, populate a partial tag table with the first authentication tag and set a first valid bit and, separately, the second authentication tag and set a second valid bit, and combine the first authentication tag and the second authentication tag into the resultant authentication tag in response to the first valid bit and the second valid bit being set. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the accelerator circuit is to, in response to the descriptor, populate the partial tag table with a first value of the hash key to a power of a number of the first plurality of cipher blocks, and with a second value of the hash key to a power of a number of the second plurality of cipher blocks, and combine the first authentication tag and the second authentication tag into the resultant authentication tag based at least in part on the first value and the second value. ### Claim 5 (depends on 2) The apparatus of claim 2, wherein the descriptor comprises at least one field that indicates the first plurality of cipher blocks is to be read in the encrypted order, and the second plurality of cipher blocks is to be read in the reverse order from the encrypted order. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the descriptor comprises a field that indicates the encrypted data is to be read in the reverse order from the encrypted order. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the accelerator circuit is further to, in response to the descriptor, decrypt the encrypted data into decrypted data and perform an authentication check of the decrypted data based at least in part on the resultant authentication tag for the encrypted data read in the reverse order. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the accelerator circuit is further to, in response to the descriptor, begin a decompress of the decrypted data into decompressed data without waiting for completion of the decrypt of the encrypted data into decrypted data. ### Claim 9 A method comprising: sending, by a hardware processor core of a system, a descriptor comprising an indication of a hash key and encrypted data to be decrypted to an accelerator circuit of the system coupled to the hardware processor core; in response to receiving the descriptor, determining if the encrypted data is to be read in an encrypted order or a reverse order from the encrypted order by the accelerator circuit; in response to the determining that the encrypted data is to be read in the reverse order, generating a resultant authentication tag in the reverse order for the encrypted data based at least in part on the hash key by the accelerator circuit without reordering the encrypted data in the reverse order into the encrypted order; in response to the determining that the encrypted data is to be read in the encrypted order, generating the resultant authentication tag in the encrypted order for the encrypted data based at least in part on the hash key by the accelerator circuit; and writing the resultant authentication tag to storage. ### Claim 10 (depends on 9) The method of claim 9, further comprising, in response to receiving the descriptor: generating a first authentication tag in the encrypted order for a first plurality of cipher blocks of the encrypted data by the accelerator circuit; generating a second authentication tag in the reverse order for a second plurality of cipher blocks of the encrypted data by the accelerator circuit; and combining the first authentication tag and the second authentication tag into the resultant authentication tag. ### Claim 11 (depends on 10) The method of claim 10, further comprising, in response to receiving the descriptor: populating a partial tag table with the first authentication tag and setting a first valid bit by the accelerator circuit; and separately, populating the partial tag table with the second authentication tag and setting a second valid bit by the accelerator circuit, wherein the combining the first authentication tag and the second authentication tag into the resultant authentication tag is in response to the first valid bit and the second valid bit being set. ### Claim 12 (depends on 11) The method of claim 11, further comprising, in response to receiving the descriptor: populating the partial tag table with a first value of the hash key to a power of a number of the first plurality of cipher blocks by the accelerator circuit; and populating the partial tag table with a second value of the hash key to a power of a number of the second plurality of cipher blocks by the accelerator circuit, wherein the combining the first authentication tag and the second authentication tag into the resultant authentication tag is based at least in part on the first value and the second value. ### Claim 13 (depends on 10) The method of claim 10, further comprising setting the descriptor to indicate the first plurality of cipher blocks is to be read in the encrypted order, and the second plurality of cipher blocks is to be read in the reverse order from the encrypted order. ### Claim 14 (depends on 9) The method of claim 9, further comprising setting the descriptor to indicate the encrypted data is to be read in the reverse order from the encrypted order. ### Claim 15 (depends on 9) The method of claim 9, further comprising, in response to receiving the descriptor: decrypting the encrypted data into decrypted data; and performing an authentication check of the decrypted data based at least in part on the resultant authentication tag for the encrypted data read in the reverse order by the accelerator circuit. ### Claim 16 (depends on 15) The method of claim 15, further comprising, in response to receiving the descriptor, begin decompressing the decrypted data into decompressed data by the accelerator circuit without waiting for completion of the decrypting of the encrypted data into decrypted data. ### Claim 17 An apparatus comprising: a hardware processor core; a memory; and an accelerator circuit coupled to the hardware processor core and the memory, the accelerator circuit to: in response to a descriptor, comprising an indication of a hash key and encrypted data in the memory to be decrypted, from the hardware processor core, perform a determination that the encrypted data is to be read in an encrypted order or a reverse order from the encrypted order, in response to the determination that the encrypted data is to be read in the reverse order, generate a resultant authentication tag in the reverse order for the encrypted data based at least in part on the hash key without reordering the encrypted data in the reverse order into the encrypted order, and, in response to the determination that the encrypted data is to be read in the encrypted order, generate the resultant authentication tag in the encrypted order for the encrypted data based at least in part on the hash key. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the accelerator circuit is to, in response to the descriptor, generate a first authentication tag in the encrypted order for a first plurality of cipher blocks of the encrypted data, generate a second authentication tag in the reverse order for a second plurality of cipher blocks of the encrypted data, and combine the first authentication tag and the second authentication tag into the resultant authentication tag. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the accelerator circuit is to, in response to the descriptor, populate a partial tag table with the first authentication tag and set a first valid bit and, separately, the second authentication tag and set a second valid bit, and combine the first authentication tag and the second authentication tag into the resultant authentication tag in response to the first valid bit and the second valid bit being set. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the accelerator circuit is to, in response to the descriptor, populate the partial tag table with a first value of the hash key to a power of a number of the first plurality of cipher blocks, and with a second value of the hash key to a power of a number of the second plurality of cipher blocks, and combine the first authentication tag and the second authentication tag into the resultant authentication tag based at least in part on the first value and the second value. ### Claim 21 (depends on 18) The apparatus of claim 18, wherein the descriptor comprises at least one field that indicates the first plurality of cipher blocks is to be read in the encrypted order, and the second plurality of cipher blocks is to be read in the reverse order from the encrypted order. ### Claim 22 (depends on 17) The apparatus of claim 17, wherein the descriptor comprises a field that indicates the encrypted data is to be read in the reverse order from the encrypted order. ### Claim 23 (depends on 17) The apparatus of claim 17, wherein the accelerator circuit is further to, in response to the descriptor, decrypt the encrypted data into decrypted data and perform an authentication check of the decrypted data based at least in part on the resultant authentication tag for the encrypted data read in the reverse order. ### Claim 24 (depends on 23) The apparatus of claim 23, wherein the accelerator circuit is further to, in response to the descriptor, begin a decompress of the decrypted data into decompressed data without waiting for completion of the decrypt of the encrypted data into decrypted data.