# US 12,118,098 B1 · Computer processing system and method configured to effectuate lower-order masking in a higher-order masked design

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- Number: US 12,118,098 B1
- Document ID: US12118098B1
- Status: Granted
- Kind: B1
- Application number: 18/702,684
- Filed: 2023-12-08
- Granted: 2024-10-15
- Earliest claimed: 2023-12-08
- Assignees: PQSecure Technologies, LLC
- Applicants: Pqsecure Technologies, LLC
- Inventors: Abubakr Abdulgadir; Rami ElKhatib
- Web page: https://patentgrep.com/patent/US12118098B1

## CPC

- G06F 21/602: {Providing cryptographic facilities or services}
- G06F 7/764: {Masking}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A computer processing system configured to effectuate lower-order masking in a higher-order masked design that includes a DOM Multiplication gate of order M operably configured to receive M+1 data shares for each of a plurality of variables and operably configured to perform a lower order masking of N. As used herein, M is greater than N, by disabling at least one cross-domain computation of the M+1 data shares between N+1 data shares and M−N data shares. To that end, the system and method of effectuating lower-ordered masking in a higher-order masked design beneficially by being operable to disable cross-domain computations to perform the lower-order masked operations.

## Claims

### Claim 1

A computer processing system configured to effectuate lower-order masking in a higher-order masked design comprising:
a DOM Multiplication gate of order M operably configured to receive M+1 data shares for each of a plurality of variables and operably configured to perform a lower order masking of N, wherein N<M, by disabling at least one cross-domain computation of the M+1 data shares between N+1 data shares and M−N data shares.

### Claim 2 (depends on 1)

The computer processing system according to claim 1, wherein the disabling further comprises:
zeroing out input of the M−N data shares and zeroing out any completely random data input in the cross-domain computation between N+1 data shares and M−N data shares within the DOM Multiplication gate.

### Claim 3 (depends on 1)

The computer processing system according to claim 1, wherein the disabling further comprises:
disabling internal gates configured to perform the at least one cross-domain computation of the M+1 data shares between N+1 data shares and M−N data shares.

### Claim 4 (depends on 1)

The computer processing system according to claim 1, wherein the DOM Multiplication gate of the order M is operably configured to perform k lower order maskings of N0, N1, N2, . . . , Nk in parallel such that M+1≥(L+1)=(N0+1)+(N1+1)+(N2+1)+ . . . +(Nk+1) by disabling internal gates configured to perform the at least one cross-domain computation of the M+1 data shares between each of (N0+1), (N1+1), (N2+1), . . . , (Nk+1) and M−L data shares.

### Claim 5 (depends on 1)

The computer processing system according to claim 1, wherein N=0.

### Claim 6 (depends on 1)

The computer processing system according to claim 1, wherein the computer processing system is configured to perform SHA-3, Keccak, or their respective derivatives.

### Claim 7

A computer-implemented method for performing lower-order masking in a higher-order masked design comprising the steps of:
performing DOM Multiplication operation of order N inside a DOM Multiplication operation of order M inside a computer system; and
disabling at least one cross-domain computation of the M+1 data shares between N+1 data shares and M−N data shares in the DOM Multiplication operation of order M.

### Claim 8 (depends on 7)

The computer-implemented method according to claim 7, further comprising:
disabling at least one cross-domain computation of the M+1 data shares between N+1 data shares and M−N data shares by zeroing out input of the M−N data shares and zeroing out any completely random data input in the cross-domain computation between N+1 data shares and M−N data shares within the DOM Multiplication operation.

### Claim 9 (depends on 7)

The computer-implemented method according to claim 7, further comprising:
disabling at least one cross-domain computation of the M+1 data shares between N+1 data shares and M−N data shares by disabling internal gates configured to perform the at least one cross-domain computation of the M+1 data shares between N+1 data shares and M−N data shares.

### Claim 10 (depends on 7)

The computer-implemented method according to claim 7, further comprising:
performing k DOM Multiplication operations of order N0, N1, N2, . . . , Nk in parallel such that M+1≥(L+1)=(N0+1)+(N1+1)+(N2+1)+ . . . +(Nk+1) by disabling internal gates configured to perform the at least one cross-domain computation of the M+1 data shares between each of (N0+1), (N1+1), (N2+1), . . . , (Nk+1) and M−L data shares.

### Claim 11 (depends on 7)

The computer-implemented method according to claim 7, wherein N=0.

### Claim 12 (depends on 7)

The computer-implemented method according to claim 7, further comprising:
performing SHA-3, Keccak, or their respective derivatives in the computer system.