# US 12,117,956 B2 · Writes to multiple memory destinations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,117,956 B2 - Document ID: US12117956B2 - Status: Granted - Kind: B2 - Application number: 16/726,676 - Filed: 2019-12-24 - Published: 2020-04-30 - Granted: 2024-10-15 - Earliest claimed: 2019-03-04 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Mark Sean Hefty; Arlin R. Davis - Web page: https://patentgrep.com/patent/US12117956B2 ## CPC - G06F 13/4234: {being a memory bus} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/546: {Message passing systems or structures, e.g. queues} - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 21/606: {by securing the transmission between two devices or processes} - G06F 21/6227: {where protection concerns the structure of data, e.g. records, types, queries} - H04L 45/566: {Routing instructions carried by the data packet, e.g. active networks} - H04L 67/1097: for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS] - H04L 69/22: Parsing or analysis of headers - H04L 69/321: Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Examples described herein relate to configuring a target network interface to recognize packets that are to be written directly from the network interface to multiple memory destinations. A packet can include an identifier that a portion of the packet is to be written to multiple memory devices at specific addresses. The packet is validated to determine if the target network interface is permitted to directly copy the portion of the packet to memory of the target. The target network interface can perform a direct copy to multiple memory locations of a portion of the packet. ## Claims ### Claim 1 An apparatus comprising: a network interface comprising direct memory access (DMA) circuitry and circuitry configured to: access a received packet, wherein the received packet comprises a header and a payload and based on the received packet including a designation to copy a portion of the received packet to at least two destinations, wherein the designation comprises command that is positioned in the header of the received packet: copy, by at least one DMA operation of the DMA circuitry, a first portion of the payload to a first destination of the at least two destinations based on the designation and copy, by at least one DMA operation of the DMA circuitry, the first portion of the payload to a second destination of the at least two destinations based on the designation. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the circuitry is configured to: determine if the received packet includes a designation to copy the portion of the received packet to at least two destinations in a memory. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein: the packet payload includes the first portion and a second portion and based on the received packet including a designation to copy the first portion to an associated at least one destination and the second portion to an associated at least one destination, the DMA circuitry is to perform at least one copy of the first portion to the associated at least one destination and the circuitry is to perform at least one copy of the second portion to the associated at least one destination. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the first portion is different than the second portion. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein: the packet payload includes the first portion, a second portion and a third portion and based on the received packet including a designation to copy the first portion to an associated at least one destination, the second portion to an associated at least one destination, and the third portion to an associated at least one destination, the DMA circuitry is to: perform at least one copy of the first portion to the associated at least one destination, perform at least one copy of the second portion to the associated at least one destination, and perform at least one copy of the third portion to the associated at least one destination. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the command comprises one or more of: an op code to specify a multi-write operation, a number of memory regions that the portion will be written to, a size of incoming payload, or an offset into a memory region where a write is to begin. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the first destination of the at least two destinations and the second destination of the at least two destinations comprise memory addresses accessible by one or more of: an accelerator, graphics processing unit, or central processing unit. ### Claim 8 (depends on 1) The apparatus of claim 1 further comprising one or more of: a compute platform, a data center, server, rack, blade, or a host computer and the network interface is coupled to the one or more of: a compute platform, a data center, server, rack, blade, or a host computer and wherein the compute platform, a data center, server, rack, blade, or a host computer is to process the first portion. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein remote direct memory access (RDMA) queue pairs are associated with communications including the received packet, the queue pairs include at least one send queue and at least one receive queue, and the at least one receive queue is to store the received packet. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the first destination of the at least two destinations is associated with a first memory device and wherein the second destination of the at least two destinations is associated with a second memory device. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the network interface is to perform remote direct memory access (RDMA) offload. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the received packet comprises a header field associated with a multi-write remote direct memory access (RDMA). ### Claim 13 (depends on 1) The apparatus of claim 1, wherein the command is solely within the header of the received packet. ### Claim 14 (depends on 1) The apparatus of claim 1, wherein the header is based on an Ethernet standard. ### Claim 15 A method comprising: receiving a packet that comprises an indication that comprises a command to a receiver network interface to copy a portion of the packet to a first destination and to copy a second portion of the packet to a second destination, wherein the packet includes a header portion and a payload portion and wherein the packet includes at least one header field in the header portion that includes the indication; performing, by a direct memory access (DMA) operation, a copy of the portion to the first destination; and performing, by a DMA operation, a copy of the second portion to the second destination. ### Claim 16 (depends on 15) The method of claim 15, wherein the receiver network interface performs the receiving and performing the copies. ### Claim 17 (depends on 15) The method of claim 15, wherein the portion immediately precedes the second portion in the packet. ### Claim 18 (depends on 15) The method of claim 15, wherein the packet includes an indication to copy a third portion of the packet to a third destination and to copy a fourth portion of the packet to a fourth destination and comprising: performing, by a DMA operation, a copy of the third portion to the third destination and performing, by a DMA operation, a copy of the fourth portion to the fourth destination. ### Claim 19 (depends on 15) The method of claim 15, wherein the command comprises one or more of: an op code to specify a multi-write operation, a number of memory regions that a portion will be written to, a size of incoming payload, or an offset into a memory region where a write is to begin. ### Claim 20 (depends on 15) The method of claim 15, comprising processing data from the packet in the first and second destinations using one or more of: an accelerator, graphics processing unit, or central processing unit. ### Claim 21 (depends on 15) The method of claim 15, wherein the header portion is based on an Ethernet standard. ### Claim 22 At least one non-transitory computer-readable medium comprising instructions stored thereon, that when executed, causes at least one processor to: configure a network interface device to establish and use a remote direct memory access (RDMA) to cause a copy of content of a packet to multiple destinations in memory; provide a request to the network interface device to initiate forming the packet with a header that includes an indication with a command to a receiver network interface device to copy a first portion of a payload of the packet to a first destination in at least one memory device and to copy the first portion of the packet to a second destination in at least one memory device, wherein the packet includes the header and the payload, wherein the header comprises the command; and cause the network interface device to transmit a single copy of the packet to the receiver network interface device, wherein the receiver network interface device is communicatively coupled to the at least one memory device. ### Claim 23 (depends on 22) The non-transitory computer-readable medium of claim 22, wherein the indication comprises one or more of: an op code to specify a multi-write operation, a number of memory regions that content will be written to, a size of incoming payload, or an offset into a memory region where a write is to begin.