# US 12,117,953 B2 · Memory disaggregation and reallocation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,117,953 B2 - Document ID: US12117953B2 - Status: Granted - Kind: B2 - Application number: 18/421,506 - Filed: 2024-01-24 - Published: 2024-05-16 - Granted: 2024-10-15 - Earliest claimed: 2022-02-16 - Assignees: Drut Technologies Inc. - Applicants: Drut Technologies Inc. - Inventors: Jitender Miglani; Dileep Desai - Web page: https://patentgrep.com/patent/US12117953B2 ## CPC - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G06F 13/1668: {Details of memory controller} - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/4068: {Electrical coupling} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A server rack has server sleds, each including a motherboard upon which is mounted: a memory module, a cache, at least one CPU connected to the cache, a memory controller connected to the cache and the memory module, an I/O hub, and a fabric interface (FIC) having a memory bridge and optical transceivers, where this memory bridge is connected to the I/O hub through this motherboard. The rack also has a memory sled disaggregated from the server sleds and that includes: a motherboard upon which is mounted: memory modules and a FIC having a memory bridge, a memory controller and optical transceivers, wherein this memory controller is connected to these memory modules through this motherboard, and wherein this memory bridge connects the memory controller to the optical transceivers. The rack has a photonic cross-connect switch interconnected by optical fiber cables to the optical transceivers of the server and memory sleds. ## Claims ### Claim 1 At least one server rack comprising: a plurality of server sleds, each server sled comprising: a first motherboard, a CPU module mounted on the first motherboard, a first fabric interface mounted on the first motherboard and having a first memory bridge and a first plurality of optical and/or electrical transceivers, wherein the first memory bridge is coupled to the CPU module through the first motherboard; a memory sled that is disaggregated from the plurality of server sleds, the memory sled comprising: a second motherboard; a plurality of memory modules mounted on the second motherboard, a second fabric interface mounted on the second motherboard and having a second memory bridge and a memory controller and a second plurality of optical and/or electrical transceivers, wherein the memory controller is coupled to the memory modules through the second motherboard, and wherein the second memory bridge connects the memory controller to the second plurality of optical and/or electrical transceivers; the first plurality of optical and/or electrical transceivers configured to interconnect through a first plurality of optical and/or electrical wires to a cross-connection switch; and the second plurality of optical and/or electrical transceivers configured to interconnect through a second plurality of optical and/or electrical wires to the cross-connection switch, wherein memory blocks of the memory sled and each of the plurality of server sleds are reconfigurable by selecting the memory sled to have the second plurality of optical and/or electrical transceivers configured to interconnect through the second plurality of optical and/or electrical wires to the cross-connect switch to any one or more of the server sleds based on the memory resources needed by each server sled. ### Claim 2 (depends on 1) The least one server rack of claim 1, wherein the first fabric interface comprises a first data path transport to convert memory bus data from the first memory bridge into a retimed parallel version of the memory bus data to be sent by the first plurality of optical and/or electrical transceivers over the cross-connect switch to a second data path transport of the second fabric interface. ### Claim 3 (depends on 1) The least one server rack of claim 1, wherein the memory sled is a first memory sled and further comprising: a second memory sled that is disaggregated from the plurality of server sleds, the second memory sled comprising: a third motherboard; a plurality of third memory modules mounted on the third motherboard, a third fabric interface mounted on the third motherboard and having a third memory bridge and a third memory controller and a third plurality of optical and/or electrical transceivers, wherein the third memory controller is coupled to the third memory modules through the third motherboard, and wherein the third memory bridge connects the third memory controller to the third plurality of optical and/or electrical transceivers; the third plurality of optical and/or electrical transceivers configured to interconnect through a third plurality of optical and/or electrical wires to the cross-connect switch. ### Claim 4 (depends on 3) The least one server rack of claim 3, wherein memory blocks of the first and second memory sled and each of the plurality of server sleds are reconfigurable by selecting one of the first or second memory sled to have the third plurality of optical and/or electrical transceivers configured to interconnect through the third plurality of optical and/or electrical wires to the cross-connect switch to any one or more of the server sleds based on the memory resources needed by each server sled. ### Claim 5 (depends on 3) The least one server rack of claim 3, wherein the first and second memory sled are connected through the cross-connect switch to a first one of the server sleds, wherein the first but not the second memory sled is connected through the cross-connect switch to a second one of the server sleds, and wherein the second but not the first memory sled is connected through the cross-connect switch to a third one of the server sleds. ### Claim 6 (depends on 1) The least one server rack of claim 1, wherein the memory sled includes multiple memory modules (DIMMs) that are arranged as memory blocks on a board to be associated with the memory controller such that the memory controller can be represented as a memory resource block to a fabric manager. ### Claim 7 (depends on 6) The least one server rack of claim 6, wherein each memory block can be attached or detached to a plurality of CPUs of the at least one CPU. ### Claim 8 (depends on 6) The least one server rack of claim 6, wherein multiple memory modules (DIMMs) can be accessed by more than one CPU of the at least one CPU when connected from different CPUs of the at least one CPU as a shared memory resource. ### Claim 9 (depends on 1) The least one server rack of claim 1, wherein converting memory bus data from the first memory bridge into the retimed parallel version of the memory bus data includes combining address bus data, interface bus data and devices identification bus data of the memory bus data into a data-path-bundle for a selected number of SERDES lanes of the retimed parallel version that is in a different timing domain than the memory bus data. ### Claim 10 At least one server rack comprising: a plurality of server sleds, each server sled comprising: a first motherboard, a CPU module mounted on the first motherboard, a first fabric interface mounted on the first motherboard and having a first memory bridge and a first plurality of optical and/or electrical transceivers, wherein the first memory bridge is coupled to the CPU module through the first motherboard; a memory sled that is disaggregated from the plurality of server sleds, the memory sled comprising: a second motherboard; a plurality of memory modules mounted on the second motherboard, a second fabric interface mounted on the second motherboard and having a second memory bridge and a memory controller and a second plurality of optical and/or electrical transceivers, wherein the memory controller is coupled to the memory modules through the second motherboard, and wherein the second memory bridge connects the memory controller to the second plurality of optical and/or electrical transceivers; the first plurality of optical and/or electrical transceivers configured to interconnect through a first plurality of optical and/or electrical wires to a cross-connection switch; and the second plurality of optical and/or electrical transceivers configured to interconnect through a second plurality of optical and/or electrical wires to the cross-connection switch; wherein the first fabric interface comprises a first data path transport to convert memory bus data from the first memory bridge into a retimed parallel version of the memory bus data to be sent by the first plurality of optical and/or electrical transceivers through the second plurality of optical and/or electrical wires to the cross-connect switch; and wherein converting memory bus data from the memory bridge into the retimed parallel version of the memory bus data includes combining address bus data, interface bus data and devices identification bus data of the memory bridge into a data-path-bundle for a selected number of serializer/deserializer (SERDES) lanes of the retimed parallel version that is in a different timing domain than the memory bridge data. ### Claim 11 (depends on 10) The least one server rack of claim 10, wherein memory blocks of the memory sled and each of the plurality of server sleds are reconfigurable by selecting the memory sled to be connected through the cross-connect switch to any one or more of the server sleds based on the memory resources needed by each server sled. ### Claim 12 (depends on 10) The least one server rack of claim 10, wherein the memory sled is a first memory sled and further comprising: a second memory sled that is disaggregated from the plurality of server sleds, the second memory sled comprising: a third motherboard; a plurality of third memory modules mounted on the third motherboard, a third fabric interface mounted on the third motherboard and having a third memory bridge and a third memory controller and a third plurality of optical and/or electrical transceivers, wherein the third memory controller is coupled to the third memory modules through the third motherboard, and wherein the third memory bridge connects the third memory controller to the third plurality of optical and/or electrical transceivers; the third plurality of optical and/or electrical transceivers configured to interconnect through a third plurality of optical and/or electrical wires to the cross-connect switch. ### Claim 13 (depends on 12) The least one server rack of claim 12, wherein memory blocks of the first and second memory sled and each of the plurality of server sleds are reconfigurable by selecting one of the first or second memory sled to have the third plurality of optical and/or electrical transceivers configured to interconnect through the third plurality of optical and/or electrical wires to the cross-connect switch to any one or more of the server sleds based on the memory resources needed by each server sled. ### Claim 14 (depends on 12) The least one server rack of claim 12, wherein the first and second memory sled are connected through the cross-connect switch to a first one of the server sleds, wherein the first but not the second memory sled is connected through the cross-connect switch to a second one of the server sleds, and wherein the second but not the first memory sled is connected through the cross-connect switch to a third one of the server sleds. ### Claim 15 (depends on 10) The least one server rack of claim 10, wherein the memory sled includes multiple memory modules (DIMMs) that are arranged as memory blocks on a board to be associated with the memory controller such that the memory controller can be represented as a memory resource block to a fabric manager. ### Claim 16 (depends on 15) The least one server rack of claim 15, wherein each memory block can be attached or detached to a plurality of CPUs of the at least one CPU. ### Claim 17 (depends on 15) The least one server rack of claim 15, wherein multiple memory modules (DIMMs) can be accessed by more than one CPU of the at least one CPU when connected from different CPUs of the at least one CPU as a shared memory resource.