# US 12,117,949 B2 · Configurable cryptographic processor with integrated DMA interface for secure data handling > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,117,949 B2 - Document ID: US12117949B2 - Status: Granted - Kind: B2 - Application number: 18/364,786 - Filed: 2023-08-03 - Published: 2023-11-30 - Granted: 2024-10-15 - Earliest claimed: 2021-05-26 - Assignees: Stmicroelectronics Application GmbH - Applicants: STMicroelectronics Application GMBH - Inventors: Rolf Nandlinger; Roberto Colombo - Web page: https://patentgrep.com/patent/US12117949B2 ## CPC - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 9/30105: {Register structure} - G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 21/602: {Providing cryptographic facilities or services} - G06F 21/72: in cryptographic circuits - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory. ## Claims ### Claim 1 A cryptographic processor, comprising: a plurality of input data registers configured to store a block of data having a plurality of bytes, the number of input data registers corresponding to a first number of registers; a plurality of output data registers configured to store a block of processed data, the number of output data registers corresponding to the first number of registers; a first programmable control register configured to store a first configuration data; a cryptographic processing circuit configured to: process the data stored in the input data registers as a function of the first configuration data stored in the first programmable control register, store respective processed data to the output data registers, and generate a first control signal in response to the processed data being stored in the output data registers; a first Direct-Memory-Access (DMA) interface circuit configured to generate a first request signal requesting that a new block of data be transferred to the input data registers, the first DMA interface circuit configured to: assert the first request signal as a function of the first configuration data stored in the first programmable control register and in response to a synchronization signal, and de-assert the first request signal in response to a first acknowledge signal; and a second DMA interface circuit configured to generate a second request signal requesting that a block of processed data be transferred from the output data registers, the second DMA interface circuit configured to: assert the second request signal as a function of the first control signal, de-assert the second request signal in response to a second acknowledge signal, and assert the synchronization signal in response to the second acknowledge signal. ### Claim 2 (depends on 1) The cryptographic processor of claim 1, wherein the block of data is 16 bytes. ### Claim 3 (depends on 1) The cryptographic processor of claim 1, wherein the cryptographic processing circuit is an Advanced Encryption Standard (AES) processing circuit. ### Claim 4 (depends on 1) The cryptographic processor of claim 1, wherein the cryptographic processor is part of a processing system within an integrated circuit. ### Claim 5 (depends on 1) The cryptographic processor of claim 1, wherein the cryptographic processor is part of a processing system in a device comprising a plurality of processing systems coupled via a communication system. ### Claim 6 (depends on 5) The cryptographic processor of claim 5, wherein the device is a vehicle. ### Claim 7 (depends on 5) The cryptographic processor of claim 5, wherein the processing system comprises a microprocessor, a memory controller, a second communication system, the cryptographic processor, a first DMA channel, a second DMA channel, and a request control circuit. ### Claim 8 A method of operating a processing system to transmit data via the processing system, the method comprising: storing data to be transmitted to a memory of the processing system; transferring the stored data via a first Direct-Memory-Access (DMA) channel from the memory to input data registers of a cryptographic co-processor; storing, by a plurality of input data registers of the cryptographic co-processor, a block of data having a plurality of bytes, the number of input data registers corresponding to a first number of registers; storing, by a plurality of output data registers of the cryptographic co-processor, a block of processed data, the number of output data registers corresponding to the first number of registers; storing first configuration data by a first programmable control register of the cryptographic co-processor; processing, by a cryptographic processing circuit of the cryptographic co-processor, the data stored in the input data registers as a function of the first configuration data stored in the first programmable control register; storing, by the cryptographic processing circuit, respective processed data to the output data registers; generating, by the cryptographic processing circuit, a first control signal in response to the processed data being stored in the output data registers; generating, by a first Direct-Memory-Access (DMA) interface circuit of the cryptographic co-processor, a first request signal requesting that a new block of data be transferred to the input data registers, the generating comprising: asserting the first request signal as a function of the first configuration data stored in the first programmable control register and in response to a synchronization signal, and de-asserting the first request signal in response to a first acknowledge signal; and generating, by a second DMA interface circuit of the cryptographic co-processor, a second request signal requesting that a block of processed data be transferred from the output data registers, the generating comprising: asserting the second request signal as a function of the first control signal, de-asserting the second request signal in response to a second acknowledge signal, and asserting the synchronization signal in response to the second acknowledge signal. ### Claim 9 (depends on 8) The method of claim 8, wherein the block of data is 16 bytes. ### Claim 10 (depends on 8) The method of claim 8, wherein the cryptographic processing circuit is an Advanced Encryption Standard (AES) processing circuit. ### Claim 11 (depends on 8) The method of claim 8, wherein the processing system is integrated within an integrated circuit. ### Claim 12 (depends on 8) The method of claim 8, wherein the processing system is a system in a device comprising a plurality of processing systems coupled via a further communication system. ### Claim 13 (depends on 12) The method of claim 12, wherein the device is a vehicle. ### Claim 14 (depends on 8) The method of claim 8, wherein the processing system comprises a microprocessor, a memory controller, a second communication system, the cryptographic co-processor, the first DMA channel, a second DMA channel, and a request control circuit. ### Claim 15 A device comprising a cryptographic processor, the cryptographic processor comprising: a plurality of input data registers configured to store a block of data having a plurality of bytes, the number of input data registers corresponding to a first number of registers; a plurality of output data registers configured to store a block of processed data, the number of output data registers corresponding to the first number of registers; a first programmable control register configured to store a first configuration data; a cryptographic processing circuit configured to: process the data stored in the input data registers as a function of the first configuration data stored in the first programmable control register, store respective processed data to the output data registers, and generate a first control signal in response to the processed data being stored in the output data registers; a first Direct-Memory-Access (DMA) interface circuit configured to generate a first request signal requesting that a new block of data be transferred to the input data registers, the first DMA interface circuit configured to: assert the first request signal as a function of the first configuration data stored to the first programmable control register and in response to a synchronization signal, and de-assert the first request signal in response to a first acknowledge signal; and a second DMA interface circuit configured to generate a second request signal requesting that a block of processed data be transferred from the output data registers, the second DMA interface circuit configured to: assert the second request signal as a function of the first control signal, de-assert the second request signal in response to a second acknowledge signal, and assert the synchronization signal in response to the second acknowledge signal. ### Claim 16 (depends on 15) The device of claim 15, wherein the block of data is 16 bytes. ### Claim 17 (depends on 15) The device of claim 15, wherein the cryptographic processing circuit is an Advanced Encryption Standard (AES) processing circuit. ### Claim 18 (depends on 15) The device of claim 15, wherein the cryptographic processor is part of a processing system within an integrated circuit. ### Claim 19 (depends on 15) The device of claim 15, wherein the cryptographic processor is part of a processing system in the device comprising a plurality of processing systems coupled via a communication system. ### Claim 20 (depends on 19) The device of claim 19, wherein the device is a vehicle.