# US 12,117,948 B2 · Data processing unit with transparent root complex > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,117,948 B2 - Document ID: US12117948B2 - Status: Granted - Kind: B2 - Application number: 17/976,909 - Filed: 2022-10-31 - Published: 2024-05-02 - Granted: 2024-10-15 - Earliest claimed: 2022-10-31 - Assignees: Mellanox Technologies, Ltd. - Applicants: Mellanox Technologies, Ltd. - Inventors: Liran Liss; Rabia Loulou; Idan Burstein; Tzuriel Katoa - Web page: https://patentgrep.com/patent/US12117948B2 ## CPC - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus. ## Claims ### Claim 1 Computing apparatus, comprising: a central processing unit (CPU); a root complex connected to the CPU and to a first peripheral component bus, which has a first address space and has at least a first downstream port for connection to at least one peripheral device, wherein the root complex is to present the at least one peripheral device to the CPU in the first address space; and switching logic, which has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, the second peripheral component bus having a second address space, wherein the switching logic is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in the second address space of the second peripheral component bus. ### Claim 2 (depends on 1) The apparatus according to claim 1, wherein the switching logic comprises a virtual switch. ### Claim 3 (depends on 1) The apparatus according to claim 1, wherein the switching logic is to present the peripheral device as a physical function in the address space of the second peripheral component bus. ### Claim 4 (depends on 3) The apparatus according to claim 3, wherein the peripheral device is to expose a virtual function on the first peripheral component bus, and the switching logic is to present the virtual function as the physical function in the address space of the second peripheral component bus. ### Claim 5 (depends on 1) The apparatus according to claim 1, wherein the switching logic is to present the peripheral device as a virtual function in the address space of the second peripheral component bus. ### Claim 6 (depends on 1) The apparatus according to claim 1, wherein the peripheral device comprises a data storage device. ### Claim 7 (depends on 1) The apparatus according to claim 1, wherein the peripheral device comprises a network interface controller (NIC). ### Claim 8 (depends on 1) The apparatus according to claim 1, wherein the switching logic is to receive a bus transaction via the upstream port referencing the second address space of the second peripheral component bus and directed to the peripheral device, to translate the bus command to the first address space, and to transmit the translated bus command over the first peripheral component bus. ### Claim 9 (depends on 1) The apparatus according to claim 1, wherein the switching logic is to reserve a segment of the address space for a dummy device, to enable hot-plugging of a further peripheral device in the reserved segment. ### Claim 10 A method for computing, comprising: providing a peripheral device server comprising a central processing unit (CPU) and a root complex connected to a first peripheral component bus having a first address space; connecting a peripheral device to a first downstream port on the first peripheral component bus, wherein the root complex presents the peripheral device to the CPU in the first address space; connecting an upstream port of the peripheral device server to a second downstream port on a second peripheral component bus of a host computer, the second peripheral component bus having a second address space; and using switching logic in the peripheral device server coupled between the upstream port and the first downstream port, presenting the peripheral device to the host computer in the second address space of the second peripheral component bus. ### Claim 11 (depends on 10) The method according to claim 10, wherein the switching logic comprises a virtual switch coupled between the upstream port and the first downstream port. ### Claim 12 (depends on 10) The method according to claim 10, wherein presenting the peripheral device comprises exposing the peripheral device as a physical function in the address space of the second peripheral component bus. ### Claim 13 (depends on 12) The method according to claim 12, wherein coupling the peripheral device comprises exposing a virtual function of the peripheral device on the first peripheral component bus, and wherein exposing the peripheral device comprises presenting the virtual function as the physical function in the address space of the second peripheral component bus. ### Claim 14 (depends on 10) The method according to claim 10, wherein presenting the peripheral device comprises exposing the peripheral device as a virtual function in the address space of the second peripheral component bus. ### Claim 15 (depends on 10) The method according to claim 10, wherein the peripheral device comprises a data storage device. ### Claim 16 (depends on 10) The method according to claim 10, wherein the peripheral device comprises a network interface controller (NIC). ### Claim 17 (depends on 10) The method according to claim 10, and comprising receiving, by the switching logic, a bus transaction via the upstream port referencing the second address space of the second peripheral component bus and directed to the peripheral device, translating the bus command to the first address space, and transmitting the translated bus command over the first peripheral component bus. ### Claim 18 (depends on 10) The method according to claim 10, and comprising reserving a segment of the address space for a dummy device, to enable hot-plugging of a further peripheral device in the reserved segment.