# US 12,117,934 B2 · Method and system for sharing memory between processors by updating shared memory space including funtionality to place processors into idle state > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,117,934 B2 - Document ID: US12117934B2 - Status: Granted - Kind: B2 - Application number: 17/218,082 - Filed: 2021-03-30 - Published: 2022-10-06 - Granted: 2024-10-15 - Earliest claimed: 2021-03-30 - Assignees: ATI Technologies ULC - Applicants: ATI Technologies ULC - Inventors: Dror Smolarsky - Web page: https://patentgrep.com/patent/US12117934B2 ## CPC - G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)} - G06F 12/0646: {Configuration or reconfiguration} - G06F 9/4418: {Suspend and resume; Hibernate and awake} - G06F 15/167: using a common memory, e.g. mailbox - G06F 2212/1044: Space efficiency improvement - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A method and system for sharing memory in a computer system includes placing one or more processors in the computer system in an idle state. The one or more processors are queried for associated memory space, and a shared physical memory address space is updated, wherein each processor in the system has access to the physical memory in the shared physical memory address space. The one or more processors is removed from the idle state, and work is submitted to the one or more processors for execution. ## Claims ### Claim 1 A method for sharing memory in a computer system, comprising: placing one or more processors in the computer system in an idle state; querying the one or more processors for an invisible memory associated with each of the one or more processors; updating a shared physical memory address space to include the invisible memory associated with at least one of the one or more processors wherein data stored in the shared physical memory address space is accessible to each of the one or more processors; removing the one or more processors from the idle state upon performing the updating of the shared physical memory address space; and submitting work to the one or more processors for execution. ### Claim 2 (depends on 1) The method of claim 1, wherein the placing of the one or more processors in the idle state is performed upon a system startup of the computer system. ### Claim 3 (depends on 1) The method of claim 1, further comprising connecting an additional processor to the one or more processors of the computer system. ### Claim 4 (depends on 3) The method of claim 3, further comprising placing only the additional processor in the idle state, querying only the additional processor for invisible memory associated with the additional processor, and removing the additional processor from the idle state upon updating the shared physical memory address space. ### Claim 5 (depends on 3) The method of claim 3, further comprising updating the shared physical memory address space without placing the additional processor into the idle state. ### Claim 6 (depends on 1) The method of claim 1, further comprising disconnecting a particular processor among the one or more processors from the computer system. ### Claim 7 (depends on 6) The method of claim 6, further comprising updating the shared physical memory address space based upon the particular processor being disconnected. ### Claim 8 (depends on 7) The method of claim 7, further comprising submitting work for disconnecting the particular processor to another processor among the one or more processors. ### Claim 9 (depends on 1) The method of claim 1, further comprising each of the one or more processors: submitting an index relating to each processor and an amount of available memory space for sharing in the shared physical memory address space. ### Claim 10 A computer system, comprising: a memory; one or more processors communicatively coupled to and the memory, each processor including a processor specific memory; and a first processor communicatively coupled to the one or more processors, wherein the first processor is configured to: place the one or more processors in an idle state; query the one or more processors for invisible memory associated with each of the one or more processors; update a shared physical memory address space to include the invisible memory associated with at least one of the one or more processors, wherein data stored in the shared physical memory address space is accessible to each of the one or more processors; remove the one or more processors from the idle state upon updating of the shared physical memory address space; and submit work to the one or more processors for execution. ### Claim 11 (depends on 10) The computer system of claim 10, wherein the first processor is configured to place the one or more processors in the idle state upon a system startup of the computer system. ### Claim 12 (depends on 10) The computer system of claim 10, wherein the first processor is configured to detect an additional processor has been added to one or more processors of the computer system. ### Claim 13 (depends on 12) The computer system of claim 12, wherein the first processor is configured to place only the additional processor in the idle state, query only the additional processor for invisible memory associated with the additional processor, and remove the additional processor from the idle state upon updating the shared physical memory address space. ### Claim 14 (depends on 12) The computer system of claim 12, wherein the first processor is configured to update the shared physical memory address space without placing the additional processor into the idle state. ### Claim 15 (depends on 10) The computer system of claim 10, further wherein the first processor is configured to detect a particular processor among the one or more processors is disconnected from the computer system. ### Claim 16 (depends on 15) The computer system of claim 15, wherein the first processor is configured to update the shared physical memory address space based upon the particular processor being disconnected. ### Claim 17 (depends on 16) The computer system of claim 16, wherein the first processor is configured to submit work for disconnecting processor to another processor among the one or more processors of the computer system. ### Claim 18 (depends on 10) The computer system of claim 10, wherein each processor among the one or more processors submits an index relating to each processor and an amount of available memory space for sharing in the shared physical memory address space. ### Claim 19 A non-transitory computer-readable medium for sharing memory, the non-transitory computer-readable medium having instructions recorded thereon, that when execute by a processor, cause the processor to perform operations including: placing one or more processors in a computer system in an idle state; querying the one or more processors for an invisible memory associated with each of the one or more processors; updating a shared physical memory address space to include the invisible memory associated with at least one of the one or more processors, wherein data stored in the shared physical memory address space is accessible to each of the one or more processors; removing the one or more processors from the idle state upon performing the updating of the shared physical memory address space; and submitting work to the one or more processors for execution. ### Claim 20 (depends on 19) The non-transitory computer-readable medium of claim 19, further comprising: connecting or disconnecting a particular processor from the one or more processors of the computer system, and updating the shared physical memory address space based upon the particular processor being connected or disconnected.