# US 12,117,933 B2 · Techniques for supporting large frame buffer apertures with better system compatibility

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- Number: US 12,117,933 B2
- Document ID: US12117933B2
- Status: Granted
- Kind: B2
- Application number: 17/117,033
- Filed: 2020-12-09
- Published: 2022-06-09
- Granted: 2024-10-15
- Earliest claimed: 2020-12-09
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Paul Blinzer
- Web page: https://patentgrep.com/patent/US12117933B2

## CPC

- G06F 12/0646: {Configuration or reconfiguration}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06T 1/60: Memory management
- G09G 5/363: {Graphics controllers}
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G09G 2352/00: Parallel handling of streams of display data
- G09G 2360/08: Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
- G09G 2360/121: using a cache memory
- G09G 2360/122: Tiling
- G09G 2360/18: Use of a frame buffer in a display terminal, inclusive of the display panel
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A technique for accessing accelerated processing device (“APD”) memory is provided. The technique includes identifying whether to activate one or both of a first direct mapping unit and a second direct mapping unit, wherein the first direct mapping unit is associated with a small address size and the second direct mapping unit is associated with a large address size; activating the identified one or both of the first direct mapping unit and the second direct mapping unit; and accessing memory of the accelerated processing device using the one or both of the first direct mapping unit and the second direct mapping unit.

## Claims

### Claim 1

A method for accessing accelerated processing device (“APD”) memory, the method comprising: for a first set of memory addresses provided via a small address base address register of the APD, mapping the first set of memory addresses to a first portion of a memory of the APD in a tiled manner, wherein the small address base address register is configured to be accessed with addresses of a first size; accessing the memory of the APD according to the first mapping and the first set of memory addresses, wherein the accessing includes accessing in the tiled manner, in which a first address of the first set of memory addresses maps to an end of a tile in the memory of the APD and in which a second address immediately subsequent to the first address maps to a beginning of the tile; for a second set of memory addresses provided via a large address base address register of the APD, mapping the second set of memory addresses to a second portion of the memory of the APD, wherein the second portion is larger than the first portion, wherein the large address base address register is configured to be accessed with addresses of a second size that is larger than the first size; and accessing the memory of the APD according to the second mapping and the second set of memory addresses.

### Claim 2 (depends on 1)

The method of claim 1, wherein accessing the memory of the APD comprises converting an address of an address space of a processor that is external to the APD into an address space of the APD, as specified by the first mapping and the second mapping.

### Claim 3 (depends on 1)

The method of claim 1, further comprising determining when to access the memory according to the first mapping or the second mapping is performed based on determining whether a firmware or an operating system is capable of operating according to the large address size.

### Claim 4 (depends on 3)

The method of claim 3, further comprising: in response to determining that the firmware or the operating system are capable of operating according to the large address size, mapping the second set of memory addresses to the second portion of the memory of the APD.

### Claim 5 (depends on 3)

The method of claim 3, further comprising: in response to determining that the firmware or the operating system are not capable of operating according to the large address size, mapping the first set of memory addresses to the first portion of a memory of the APD.

### Claim 6

A computing device, comprising: one or more memories configured to store instructions; and a processor configured to execute the instructions to access accelerated processing device (“APD”) memory, by: for a first set of memory addresses provided via a small address base address register of the APD, map the first set of memory addresses to a first portion of a memory of the APD in a tiled manner, wherein the small address base address register is configured to be accessed with addresses of a first size; access the memory of the APD according to the first mapping and the first set of memory addresses, wherein the accessing includes accessing in the tiled manner, in which a first address of the first set of memory addresses maps to an end of a tile in the memory of the APD and in which a second address immediately subsequent to the first address maps to a beginning of the tile; for a second set of memory addresses provided via a large address base address register of the APD, map the second set of memory addresses to a second portion of the memory of the APD, wherein the second portion is larger than the first portion, wherein the large address base address register is configured to be accessed with addresses of a second size that is larger than the first size; and access the memory of the APD according to the second mapping and the second set of memory addresses.

### Claim 7 (depends on 6)

The computing device of claim 6, wherein accessing the memory of the APD comprises converting an address of an address space of a processor that is external to the APD into an address space of the APD, as specified by the first mapping and the second mapping.

### Claim 8 (depends on 6)

The computing device of claim 6, wherein the processor is further configured to determining when to access the memory according to the first mapping or the second mapping is performed based on determining whether a firmware or an operating system is capable of operating according to the large address size.

### Claim 9 (depends on 8)

The computing device of claim 8, wherein the instructions further cause the processor to: in response to determining that the firmware or the operating system are capable of operating according to the large address size, map the second set of memory addresses to the second portion of the memory of the APD.

### Claim 10 (depends on 8)

The computing device of claim 8, wherein the instructions further cause the processor to: in response to determining that the firmware or the operating system are not capable of operating according to the large address size, map the first set of memory addresses to the first portion of a memory of the APD.

### Claim 11

A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations comprising: for a first set of memory addresses provided via a small address base address register of an accelerated processing device (“APD”), map the first set of memory addresses to a first portion of a memory of the APD in a tiled manner, wherein the small address base address register is configured to be accessed with addresses of a first size; access the memory of the APD according to the first mapping and the first set of memory addresses, wherein the accessing includes accessing in the tiled manner, in which a first address of the first set of memory addresses maps to an end of a tile in the memory of the APD and in which a second address immediately subsequent to the first address maps to a beginning of the tile; for a second set of memory addresses provided via a large address base address register of the APD, map the second set of memory addresses to a second portion of the memory of the APD, wherein the second portion is larger than the first portion, wherein the large address base address register is configured to be accessed with addresses of a second size that is larger than the first size; and access the memory of the APD according to the second mapping and the second set of memory addresses.

### Claim 12 (depends on 11)

The non-transitory computer-readable medium of claim 11, wherein accessing the memory of the APD comprises converting an address of an address pace of a processor that is external to the APD into an address space of the APD, as specified by the first mapping and the second mapping.

### Claim 13 (depends on 1)

The method of claim 1, wherein the first portion of the memory of the APD is included within the second portion of the memory.

### Claim 14 (depends on 1)

The method of claim 1, wherein the second portion of the memory includes a non-aperture area accessed via a direct memory access mechanism.

### Claim 15 (depends on 1)

The method of claim 1, wherein the first set of memory addresses are smaller than the second set of memory addresses.

### Claim 16 (depends on 1)

The method of claim 1, wherein the mapping the first set of memory addresses to the first portion, the accessing the memory of the APD according to the first mapping, the mapping the second set of memory addresses to the second portion, and the accessing the memory of the APD according to the second mapping occurs in an overlapping time period.

### Claim 17 (depends on 6)

The computing device of claim 6, wherein the first portion of the memory of the APD is included within the second portion of the memory.

### Claim 18 (depends on 6)

The computing device of claim 6, wherein the second portion of the memory includes a non-aperture area accessed via a direct memory access mechanism.

### Claim 19 (depends on 6)

The computing device of claim 6, wherein the first set of memory addresses are smaller than the second set of memory addresses.

### Claim 20 (depends on 6)

The computing device of claim 6, wherein the mapping the first set of memory addresses to the first portion, the accessing the memory of the APD according to the first mapping, the mapping the second set of memory addresses to the second portion, and the accessing the memory of the APD according to the second mapping occurs in an overlapping time period.