# US 12,117,930 B2 · Computer architecture with disaggregated memory and high-bandwidth communication interconnects

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- Number: US 12,117,930 B2
- Document ID: US12117930B2
- Status: Granted
- Kind: B2
- Application number: 18/096,740
- Filed: 2023-01-13
- Published: 2024-03-07
- Granted: 2024-10-15
- Earliest claimed: 2022-09-06
- Assignees: Luminous Computing, Inc.
- Applicants: Luminous Computing, Inc.
- Inventors: David Cureton Baker; Ari Novack; Donovan Popps; Benjamin Wiley Melton; Bryan Cope; Mark Baur; Anahita Shayesteh
- Web page: https://patentgrep.com/patent/US12117930B2

## CPC

- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)}
- G06F 13/1668: {Details of memory controller}
- H04Q 11/0005: {Switch and router aspects}
- G06F 12/0813: with a network or matrix configuration
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1028: Power efficiency
- G06F 2212/1056: Simplification
- G06F 2212/202: Non-volatile memory
- G06F 2212/254: Distributed memory
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04Q: SELECTING (switches, relays, selectors H01H; wireless communication networks H04W)

## Abstract

Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and/or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.

## Claims

### Claim 1

A computer system comprising:
a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a central processing unit;
a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and/or write requests for the data to the plurality of memory aggregation devices;
a switching system configured to provide any to any switching of the data signals between the plurality of computational devices and the plurality of memory aggregation devices; and
a plurality of communication links, the plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices via the switching system for transferring the data therebetween;
wherein the plurality of computational devices are configured to read/write multiple read/write requests simultaneously in parallel across the unified contiguous memory address space in the plurality of random access memory modules via the plurality of memory aggregation devices.

### Claim 2 (depends on 1)

The computer system according to claim 1, further comprising:
bridge devices configured to connect to a computer motherboard interface configured for converting the data between electrical signals in packet form from a host computer and optical signals in packet form, compatible with the plurality of communication links.

### Claim 3 (depends on 1)

The computer system according to claim 1, wherein the plurality of communication links connected to the plurality of memory aggregation devices provide substantially all of an available read/write bandwidth of the plurality of random access memory modules to be accessed simultaneously.

### Claim 4 (depends on 1)

The computer system according to claim 1, wherein one or more of the plurality of communication links comprises a transmitter optical link and a receiver optical link.

### Claim 5 (depends on 4)

The computer system according to claim 4, wherein each transmitter optical link and each receiver optical link comprises a serializer and a first transducer for converting the data from parallel electrical signals to serial optical signals for transmission on an optical waveguide;
and a deserializer and second transducer for converting the serial optical signals into parallel electrical signals at the computational devices and the memory aggregation devices.

### Claim 6 (depends on 1)

The computer system according to claim 1, wherein each computational device includes a memory copy engine configured to move the data over the communication links from any memory in any of the plurality of computational devices, the plurality of memory aggregation devices and the plurality of random access memory modules to anywhere in the plurality of random access memory modules.

### Claim 7 (depends on 6)

The computer system according to claim 6, wherein each memory copy engine is configured to divide transfers of data into packets and to dispatch the packets over multiple communication links in parallel and substantially simultaneously to a plurality of the plurality of memory aggregation devices for uniformly storing in a plurality of the plurality of random access memory modules.

### Claim 8 (depends on 6)

The computer system according to claim 6, wherein the plurality of computational devices comprises at least 8 computational devices;
wherein the plurality of memory aggregation devices comprises at least 8 memory aggregation devices;
wherein each memory copy engine is configured to launch at least 16 of the memory read and/or write requests in parallel and substantially simultaneously to each memory aggregation device over the communication links there between.

### Claim 9 (depends on 6)

The computer system according to claim 6, wherein at least some of the memory copy engines are co-located with processing cores that are configured to compute data.

### Claim 10 (depends on 6)

The computer system according to claim 6, wherein at least some of memory copy engines are co-located with bridge devices that are configured to communicate with other processors using a standard interface.

### Claim 11 (depends on 6)

The computer system according to claim 6, wherein the memory copy engines are configured to access greater than ⅔ of an available read/write bandwidth of the plurality of random access memory modules in parallel and uniformly.

### Claim 12 (depends on 6)

The computer system according to claim 6, wherein the memory copy engines are configured for memory interleaving, which is globally applied across all of the plurality of memory modules via the plurality of memory aggregation devices.

### Claim 13 (depends on 6)

The computer system according to claim 6, wherein a combination of the memory copy engines, the plurality of memory aggregation devices, and the switching system, provide a uniform memory to all of the plurality of memory copy engines.

### Claim 14 (depends on 1)

The computer system according to claim 1, wherein the switching system comprises a plurality of switch devices, one switch device for each of the plurality of computational devices.

### Claim 15 (depends on 14)

The computer system according to claim 14, wherein each switch of the plurality of switch devices includes at least 4 switch planes;
wherein each computational device includes at least 4 communication links extending to each switch device, one communication link to each switch plane;
wherein each memory aggregation device has at least 4 communication links extending thereto from one of the switch devices, one communication link from each of the switch planes.

### Claim 16 (depends on 15)

The computer system according to claim 15, wherein the plurality of random access memory modules include 4-8 random access memory modules per memory aggregation device.

### Claim 17 (depends on 16)

The computer system according to claim 16, wherein the plurality of random access memory modules comprise at least 10 TB of DRAM memory.

### Claim 18 (depends on 15)

The computer system according to claim 15, wherein at least one of the plurality of switch devices is integrated on a same combination chip as at least one of the plurality of computational devices.

### Claim 19 (depends on 18)

The computer system according to claim 18, wherein the data is bussed in one source clocked data bus that runs around a periphery of each combination chip, whereby no paths cross through the middle of the combination chip.

### Claim 20 (depends on 1)

The computer system according to claim 1, wherein greater than ⅔ of available random access memory in the plurality of random access modules is accessible via the plurality of memory aggregation devices accessible via the plurality of communication links.