# US 12,117,903 B2 · FPGA acceleration system for MSR codes

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- Number: US 12,117,903 B2
- Document ID: US12117903B2
- Status: Granted
- Kind: B2
- Application number: 18/223,019
- Filed: 2023-07-17
- Published: 2023-11-16
- Granted: 2024-10-15
- Earliest claimed: 2018-12-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Mian Qin; Joo Hwan Lee; Rekha Pitchumani; Yang Seok Ki
- Web page: https://patentgrep.com/patent/US12117903B2

## CPC

- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

## Claims

### Claim 1

An apparatus comprising:
a host interface circuit configured to receive first instruction, wherein the first instruction instructs the apparatus to perform computations associated with data elements stored by a storage system;
a memory interface circuit configured to receive the data elements from a storage system; and
computation circuit configured to perform at least a portion of the computations, wherein the computation circuit is configurable based upon a number of data nodes associated with the data elements, and wherein the data nodes comprise storage devices.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the storage system comprises a distributed storage system.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the memory interface circuit is configured to write an output of the computation circuit to an external memory.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the number of data nodes are part of the storage system; and
wherein a data node from the number of data nodes stores a portion of the data elements at a second device.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the computation circuit comprises:
a one or more multiplication circuits.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the multiplication circuits comprise lookup tables.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the computation circuit is reprogrammable by a host device.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the computation circuit includes a coefficients table.

### Claim 9

A method comprising:
receiving, by a host interface circuit in an apparatus, a first instruction, wherein the first instruction instructs the apparatus to perform computations associated with data elements stored by a storage system;
receiving, by a memory interface circuit, the data elements from a storage system; and
performing, by a computation circuit, at least a portion of the computations, where the computation circuit is configurable based upon a number of data nodes associated with the data elements, and wherein the data nodes comprise storage devices.

### Claim 10 (depends on 9)

The method of claim 9, wherein the storage system comprises a distributed storage system.

### Claim 11 (depends on 9)

The method of claim 9, wherein the memory interface circuit is configured to write an output of the computation circuit to an external memory.

### Claim 12 (depends on 9)

The method of claim 9, wherein the number of data nodes are part of the storage system; and
wherein a data node from the number of data nodes stores a portion of the data elements at a second device.

### Claim 13 (depends on 9)

The method of claim 9, wherein the computation circuit comprises:
one or more multiplication circuits.

### Claim 14 (depends on 13)

The method of claim 13, wherein the multiplication circuits comprise lookup tables.

### Claim 15 (depends on 9)

The method of claim 9, wherein the computation circuit is reprogrammable by a host device.

### Claim 16 (depends on 9)

The method of claim 9, wherein the computation circuit includes a coefficients table.

### Claim 17

A system comprising:
a memory configured to store data elements stored by a storage system; and
a reprogrammable processing device configured to perform an offloaded computation, wherein the reprogrammable processing device comprises:
a configurable pipeline that computes at least a portion of the computations and is configurable based upon a number of data nodes associated with a number of data elements, and wherein the data nodes comprise storage devices.