# US 12,117,886 B2 · System, apparatus and method for dynamically adjusting platform power and performance based on task characteristics

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- Number: US 12,117,886 B2
- Document ID: US12117886B2
- Status: Granted
- Kind: B2
- Application number: 18/449,890
- Filed: 2023-08-15
- Published: 2024-02-08
- Granted: 2024-10-15
- Earliest claimed: 2020-03-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Jianfang Zhu; Deepak Samuel Kirubakaran; Raoul Rivas Toledano; Chee Lim Nge; Rajshree Chabukswar; James Hermerding, II; Sudheer Nair; William Braun; Zhongsheng Wang; Russell Fenger; Udayan Kapaley
- Web page: https://patentgrep.com/patent/US12117886B2

## CPC

- G06F 1/329: by task scheduling
- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 1/3228: Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
- G06F 1/3231: Monitoring the presence, absence or movement of users
- G06F 1/3243: {Power saving in microcontroller unit}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/4812: {by interrupt, e.g. masked}
- G06F 9/4893: {taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

## Claims

### Claim 1

A processor, comprising:
a plurality of cores including a first plurality of cores and a second plurality of cores, the second plurality of cores comprising relatively lower power cores than the first plurality of cores;
graphics processing circuitry to perform graphics operations;
a memory controller to couple the plurality of cores and the graphics processing circuitry to a memory; and
power control circuitry to control power consumption of the plurality of cores and the graphics processing circuitry, the power control circuitry to determine background task metric information based on a first amount of time that at least one core of the plurality of cores executed background tasks during an active duration, the power control circuitry to dynamically apply a power management policy for a background mode when the background task metric information exceeds a first threshold, the power management policy for the background mode to reduce power consumption of at least the processor.

### Claim 2 (depends on 1)

The processor of claim 1, wherein to dynamically apply the power management policy includes, to apply a power limit less than a thermal design power level of the processor.

### Claim 3 (depends on 2)

The processor of claim 2, wherein to apply a power limit less than a thermal design power level of the processor includes, to reduce a frequency or voltage of the at least one core.

### Claim 4 (depends on 3)

The processor of claim 3, wherein the power control circuitry is to dynamically apply a power management policy for a responsiveness mode when a foreground task metric exceeds a responsiveness mode threshold, the power management policy for the responsiveness mode to increase performance of the processor, wherein the power management policy for the responsiveness mode comprises a power limit greater than the thermal design power level of the processor.

### Claim 5 (depends on 4)

The processor of claim 4, wherein the power control circuitry is to maintain a current power management policy when the foreground task metric does not exceed the responsiveness mode threshold.

### Claim 6 (depends on 3)

The processor of claim 3, wherein the power control circuitry is to dynamically apply the power management policy for the background mode when a user did not interact with a system including the processor within an evaluation interval.

### Claim 7 (depends on 3)

The processor of claim 3, wherein the power control circuitry is to calculate the background task metric information when a user did not interact with a system including the processor within an evaluation interval.

### Claim 8 (depends on 1)

The processor of claim 1, wherein the power control circuitry comprises a hardware feedback circuit to determine feedback information comprising an energy efficiency capability and a performance capability of the at least one core.

### Claim 9 (depends on 8)

The processor of claim 8, wherein the hardware feedback circuit is to send the feedback information to a scheduler to enable the scheduler to schedule one or more background tasks to a less performant core based at least in part on the feedback information, when a user interaction with a system including the processor is detected.

### Claim 10 (depends on 1)

The processor of claim 1, wherein the power control circuitry is to send hardware capability information of the plurality of cores of the processor to a scheduler to enable the scheduler to schedule one or more background tasks to a less performant core of the plurality of cores based at least in part on the hardware capability information, when a user interaction with a system including the processor is detected.

### Claim 11 (depends on 1)

The processor of claim 1 wherein the background task metric information comprises a ratio based on a total time a background task is scheduled on the at least one core relative to a total active time of the at least one core.

### Claim 12 (depends on 1)

The processor of claim 1, wherein the background task metric information comprises a ratio based on a first amount of time that the at least one core executed background tasks during an active duration.

### Claim 13

At least one non-transitory computer readable medium comprising instructions, which when executed by a processor, cause the processor to execute a method comprising:
determining background task metric information based on a first amount of time that at least one core of a plurality of cores of a processor executed background tasks during an active duration, the plurality of cores comprising a first plurality of cores and a second plurality of cores, the second plurality of cores comprising relatively lower power cores than the first plurality of cores; and
dynamically applying a power management policy for a background mode when the background task metric information exceeds a first threshold, the power management policy for the background mode to reduce power consumption of at least the processor.

### Claim 14 (depends on 13)

The at least one non-transitory computer readable medium of claim 13, wherein the method further comprises dynamically applying the power management policy for the background mode when a user did not interact with a system including the processor within an evaluation interval.

### Claim 15 (depends on 13)

The at least one non-transitory computer readable medium of claim 13, wherein the method further comprises calculating the background task metric information when a user did not interact with a system including the processor within an evaluation interval.

### Claim 16 (depends on 13)

The at least one non-transitory computer readable medium of claim 13, wherein the method further comprises dynamically applying a power management policy for a responsiveness mode when foreground task metric information exceeds a responsiveness mode threshold, the power management policy for the responsiveness mode to increase performance of the processor, wherein the power management policy for the responsiveness mode comprises a power limit greater than a thermal design power level of the processor.

### Claim 17 (depends on 16)

The at least one non-transitory computer readable medium of claim 16, wherein the method further comprises maintaining a current power management policy when the foreground task metric information does not exceed the responsiveness mode threshold.

### Claim 18 (depends on 13)

The at least one non-transitory computer readable medium of claim 13, wherein the method further comprises determining feedback information comprising an energy efficiency capability and a performance capability of the at least one core.

### Claim 19 (depends on 18)

The at least one non-transitory computer readable medium of claim 18, wherein the method further comprises sending the feedback information to a scheduler to enable the scheduler to schedule one or more background tasks to a less performant core based at least in part on the feedback information, when a user interaction with a system including the processor is detected.

### Claim 20 (depends on 18)

The at least one non-transitory computer readable medium of claim 18, wherein the method further comprises sending hardware capability information of the plurality of cores of the processor to a scheduler to enable the scheduler to schedule one or more background tasks to a less performant core of the plurality of cores based at least in part on the hardware capability information, when a user interaction with a system including the processor is detected.