# US 12,117,882 B2 · System and method for reducing power consumption in computing systems

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- Number: US 12,117,882 B2
- Document ID: US12117882B2
- Status: Granted
- Kind: B2
- Application number: 18/184,164
- Filed: 2023-03-15
- Published: 2024-07-18
- Granted: 2024-10-15
- Earliest claimed: 2023-01-16
- Assignees: Hamilton Sundstrand Corporation
- Applicants: Hamilton Sundstrand Corporation
- Inventors: Balaji Krishnakumar
- Web page: https://patentgrep.com/patent/US12117882B2

## CPC

- G06F 1/3228: Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 1/329: by task scheduling
- G06F 9/4887: {involving deadlines, e.g. rate based, periodic}
- G06F 9/4893: {taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A system having: a processor, wherein the processor is configured for executing a process of reducing power consumption that includes executing a first task over a first plurality of timeslots and a second task over a second plurality of timeslots, and wherein the processor is configured to: execute a real-time operating system (RTOS) process; determine that the first task is complete during a first timeslot of the first plurality of timeslots; and enter a low power mode for a reminder of the first timeslot upon determining that there is enough time to enter a low power mode during the first timeslot and a next timeslot is allocated to the first task, otherwise perform a dead-wait for the reminder of the first timeslot.

## Claims

### Claim 1

A system comprising:
a processor,
wherein the processor is configured for executing a process of reducing power consumption that includes executing a first task over a first plurality of timeslots and a second task over a second plurality of timeslots, and wherein the processor is configured to:
execute a real-time operating system (RTOS) process;
determine that the first task is complete during a first timeslot of the first plurality of timeslots; and
enter a low power mode for a remainder of the first timeslot upon determining that there is enough time to enter a low power mode during the first timeslot and a next timeslot is allocated to the first task, otherwise perform a dead-wait for the remainder of the first timeslot.

### Claim 2 (depends on 1)

The system of claim 1, wherein:
upon determining the first task is complete during the first timeslot, the processor is further configured to:
determine that the next timeslot is allocated to a next task; and
perform the dead-wait for the remainder of the first timeslot.

### Claim 3 (depends on 1)

The system of claim 1, wherein:
when the first timeslot is an initial timeslot allocated to the first task, the processor is configured to execute context switching while the processor executes the RTOS process.

### Claim 4 (depends on 1)

The system of claim 1, wherein:
entering the low power mode includes flushing of instruction cache, flushing translation look-aside buffers and disabling the instruction cache.

### Claim 5 (depends on 4)

The system of claim 4, wherein:
upon entering a timeslot that follows the first timeslot, the processor is configured to:
determine that the low power mode was entered into during the first timeslot; and
enabling the instruction cache.

### Claim 6 (depends on 5)

The system of claim 5, wherein:
after enabling the instruction cache, the processor is configured to continue to execute the RTOS process.

### Claim 7 (depends on 1)

The system of claim 1, further comprising:
a cooling mechanism operationally coupled to the processor, wherein the cooling mechanism is deactivated during the remainder of the first timeslot upon entering the low power mode.

### Claim 8 (depends on 7)

The system of claim 7, wherein:
the cooling mechanism is a fan.

### Claim 9 (depends on 7)

The system of claim 7, further comprising:
a power unit operationally coupled to the cooling mechanism and the processor.

### Claim 10 (depends on 9)

The system of claim 9, wherein:
the power unit is a battery.

### Claim 11

A method of executing a process of reducing power consumption of a processor, comprising:
executing a first task over a first plurality of timeslots and a second task over a second plurality of timeslots, and wherein the method further comprises:
executing a real-time operating system (RTOS) process;
determining that the first task is complete during a first timeslot of the first plurality of timeslots; and
entering a low power mode for a remainder of the first timeslot upon determining that there is enough time to enter a low power mode during the first timeslot and a next timeslot is allocated to the first task, otherwise performing a dead-wait for the remainder of the first timeslot.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
upon determining the first task is complete during the first timeslot, the method further comprises:
determining the next timeslot is allocated to a next task; and
performing the dead-wait for the remainder of the first timeslot.

### Claim 13 (depends on 11)

The method of claim 11, wherein:
when the first timeslot is an initial timeslot allocated to the first task, the method further comprises executing context switching while executing the RTOS process.

### Claim 14 (depends on 11)

The method of claim 11, wherein:
entering the low power mode includes flushing of instruction cache, flushing translation look-aside buffers and disabling the instruction cache.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
upon entering a timeslot that follows the first timeslot, the method includes:
determining that the low power mode was entered into during the first timeslot; and
enabling the instruction cache.

### Claim 16 (depends on 15)

The method of claim 15, wherein:
after enabling the instruction cache, the method further comprises continuing to execute the RTOS process.

### Claim 17 (depends on 16)

The method of claim 16, wherein entering the low power mode further comprises depowering a cooling mechanism that cools the processor for the remainder of the first timeslot.