# US 12,117,878 B2 · Methods and apparatus to reduce display connection latency

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,117,878 B2
- Document ID: US12117878B2
- Status: Granted
- Kind: B2
- Application number: 17/831,173
- Filed: 2022-06-02
- Published: 2022-09-15
- Granted: 2024-10-15
- Earliest claimed: 2022-06-02
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Lakshminarayana Pappu; Nausheen Ansari; Todd Witter
- Web page: https://patentgrep.com/patent/US12117878B2

## CPC

- G06F 1/266: {Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips}
- G09G 5/003: {Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092)}
- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- G06F 1/263: {Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence)}
- G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
- G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24)
- G06F 1/3209: Monitoring remote activity, e.g. over telephone lines or network connections
- G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)}
- G09G 5/005: {Adapting incoming signals to the display format of the display terminal}
- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 1/3218: of display devices
- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 9/4418: {Suspend and resume; Hibernate and awake}
- G06F 13/4081: {Live connection to bus, e.g. hot-plugging (current or voltage limitation during live insertion H02H9/004)}
- G09G 2330/023: using energy recovery or conservation
- G09G 2330/026: Arrangements or methods related to booting a display
- G09G 2370/042: for monitor identification
- G09G 2370/10: Use of a protocol of communication by packets in interfaces along the display data pipeline
- G09G 2370/22: Detection of presence or absence of input display information or of connection or disconnection of a corresponding information source
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to reduce display connection latency. An example apparatus includes interface circuitry to: detect when a display is plugged into a port; and notify processor circuitry of the detection. In response to the notification, the processor circuitry of the example apparatus moves discrete circuitry into a high power state. The example apparatus also includes discrete circuitry to, while in the high power state, identify the display.

## Claims

### Claim 1

An apparatus to reduce display connection latency, the apparatus comprising:
discrete circuitry including power-island circuitry and graphics circuitry;
connector circuitry configured to generate a wake signal in response to a display being plugged into a port;
the power-island circuitry including a Schmitt Trigger and configured to, while the graphics circuitry is powered off and the discrete circuitry is in a low power state,
filter the wake signal with the Schmitt trigger;
processor circuitry configured to, based on the filtered wake signal, cause the discrete circuitry to exit the low power state by causing the graphics circuitry to power on; and
the graphics circuitry configured to, in response to the discrete circuitry exiting the low power state, communicate with the display to obtain an identification.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the low power state is a D3hot power state.

### Claim 3 (depends on 1)

The apparatus of claim 1, further including:
an auxiliary power source configured to power the power-island circuitry in the low power state; and
a main power source configured to power the graphics circuitry on.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the power-island circuitry is configured to send an interrupt to the processor circuitry, the interrupt to request the processor circuitry cause the graphics circuitry to power on.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein to request the graphics circuitry be powered on, the power-island circuitry is configured to, in response to the filtered wake signal, send the interrupt to the processor circuitry using a Peripheral Component Interconnect Express (PCIE) protocol.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein:
the power-island circuitry is further configured to send an identification number of the graphics circuitry to the processor circuitry; and
the graphics circuitry is further configured to, in response to the discrete circuitry exiting the low power state:
receive configuration parameters from the processor circuitry; and
communicate with the display and obtain the identification by executing a device discovery protocol, the device discovery protocol based on the configuration parameters.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein to execute the device discovery protocol, the graphics circuitry is further configured to:
identify, from a plurality of ports, the port into which the display is plugged; and
determine one or more parameters of the display.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the power-island circuitry further includes
detection logic circuitry configured to, while in the low power state, provide an indication that the display is plugged into a port to the processor circuitry, the indication based on the filtered wake signal.

### Claim 9

An apparatus to reduce display connection latency, the apparatus comprising:
graphics circuitry configured to, in response to first instructions from processor circuitry to enter a low power state, power off,
power-island circuitry configured to, in response to the first instructions from the processor circuitry to enter the low power state, receive power from an auxiliary power source;
connector circuitry configured to generate a wake signal in response to a display being plugged into a port;
the power-island circuitry including a Schmitt Trigger and configured to, while in the low power state:
filter the wake with the Schmitt trigger; and
request, based on the filtered wake signal, access to a high power state; and
the graphics circuitry configured to:
exit, in response to second instructions from the processor circuitry, the low power state by powering on; and
communicate, in response to exiting the low power state, with the display to obtain an identification.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein:
the low power state is a D3hot power state; and
the high power state is a DO power state.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein the graphics circuitry and the power-island circuitry are further configured to:
receive the second instructions; and
in response to the second instructions, enter the high power state.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein:
the power-island circuitry is further configured to, while in the high power state, send an identification number of the graphics circuitry to the processor circuitry; and
the graphics circuitry is further configured to, in response to entering the high power state:
receive configuration parameters from the processor circuitry; and
communicate with the display and obtain the identification by executing a device discovery protocol, the device discovery protocol based on the configuration parameters.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein to execute the device discovery protocol, the graphics circuitry is further configured to:
identify, from a plurality of ports, the port into which the display is plugged; and
determine one or more parameters of the display.

### Claim 14 (depends on 9)

The apparatus of claim 9, wherein the power-island circuitry further includes
detection logic circuitry configured to, while in the low power state, provide an indication that the display is plugged into the port to the power-island circuitry, the indication based on the filtered wake signal.

### Claim 15 (depends on 9)

The apparatus of claim 9, wherein to request access to the high power state, the power-island circuitry is configured to, in response to the filtered wake signal, send an interrupt to the processor circuitry using a Peripheral Component Interconnect Express (PCIE) protocol.

### Claim 16

A non-transitory computer readable medium comprising instructions that, when executed, causes at least one processor to at least:
cause discrete circuitry to enter a low power state where graphics circuitry within the discrete circuitry is powered off and power-island circuitry within the discrete circuitry is powered on;
receive an indication while the discrete circuitry is in the low power state, the indication provided by the power-island circuitry, the indication based on a wake signal that is generated by connector circuitry and filtered by a Schmitt Trigger when a display is plugged into a port;
in response to the indication, cause the discrete circuitry to exit the low power state; and
the graphics circuitry configured to, in response to the discrete circuitry exiting the low power state, communicate with the display to obtain an identification.

### Claim 17 (depends on 16)

The non-transitory computer readable medium of claim 16, wherein the low power state is a D3hot state.

### Claim 18 (depends on 16)

The non-transitory computer readable medium of claim 16, wherein:
the instructions, when executed, cause the at least one processor to:
cause an auxiliary power source to power the power-island circuitry while the discrete circuitry in the low power state; and
cause a main power source to power the graphics circuitry when the discrete circuitry exits the low power state.

### Claim 19 (depends on 16)

The non-transitory computer readable medium of claim 16, wherein the power-island circuitry is further configured to request access to a high power state in response to receiving the filtered wake signal from the connector circuitry.

### Claim 20 (depends on 19)

The non-transitory computer readable medium of claim 19, wherein to request access to the high power state, the power-island circuitry is configured to, in response to the filtered wake signal, send an interrupt to the processor using a Peripheral Component Interconnect Express (PCIE) protocol.

### Claim 21 (depends on 16)

The non-transitory computer readable medium of claim 16, wherein:
the power-island circuitry is further configured to send an identification number of the graphics circuitry to the processor; and
the graphics circuitry is further configured to, in response to the discrete circuitry exiting the low power state:
receive configuration parameters from the processor; and
communicate with the display and obtain the identification by executing a device discovery protocol, the device discovery protocol based on the configuration parameters.

### Claim 22 (depends on 21)

The non-transitory computer readable medium of claim 21, wherein to execute the device discovery protocol, the graphics circuitry is further configured to:
identify, from a plurality of ports, the port into which the display is plugged; and
determine one or more parameters of the display.

### Claim 23 (depends on 16)

The non-transitory computer readable medium of claim 16, wherein the power-island circuitry further includes
detection logic circuitry configured to, while in the low power state, provide the indication to the processor, the indication based on the filtered wake signal.

### Claim 24

A method to reduce display connection latency, the method comprising:
causing, by processor circuitry, display circuitry to enter a low power state where graphics circuitry within the display circuitry is powered off and power-island circuitry within the display circuitry is powered on;
generating, by connector circuitry, a wake signal in response to a display being plugged into a port;
filtering, while the display circuitry is in the low power state and by a Schmitt Trigger, the wake signal;
causing, by the processor circuitry and based on the filtered wake signal, discrete circuitry to exit the low power state; and
communicating, by the graphics circuitry and in response to the discrete circuitry exiting the low power state, with the display to obtain an identification.

### Claim 25 (depends on 24)

The method of claim 24, further including:
receiving, by the discrete circuitry and while in the low power state, the filtered wake signal; and
requesting, by the discrete circuitry and while in the low power state, access to a high power state, the request based on the filtered wake signal.