# US 12,117,866 B2 · SOC for operating plural NPUS according to plural clock signals having multi-phases > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,117,866 B2 - Document ID: US12117866B2 - Status: Granted - Kind: B2 - Application number: 18/473,746 - Filed: 2023-09-25 - Published: 2024-01-11 - Granted: 2024-10-15 - Earliest claimed: 2023-08-24 - Assignees: Deepx Co., Ltd. - Applicants: Deepx Co., Ltd. - Inventors: Lok Won Kim; Jin Gun Song; Seong Jin Lee - Web page: https://patentgrep.com/patent/US12117866B2 ## CPC - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F 1/305: {in the event of power-supply fluctuations} - G06F 1/3243: {Power saving in microcontroller unit} - G06F 15/80: comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) - G06N 3/063: using electronic means - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A system-on-chip (SoC) may comprise a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN); a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model, each of the first NPU and the second NPU including a plurality of processing elements (PEs), the plurality of PEs including an adder, a multiplier, and an accumulator; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein a first clock signal among the one or more clock signals may be supplied to the first NPU, and a second clock signal among the one or more clock signals may be supplied to the second NPU. ## Claims ### Claim 1 A system-on-chip (SoC) comprising: a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein each of the first NPU and the second NPU includes a plurality of processing elements (PEs), and the plurality of PEs include an adder, a multiplier, and an accumulator, wherein a first clock signal among the one or more clock signals, is supplied to the first NPU, and a second clock signal among the one or more clock signals, is supplied to the second NPU, wherein at least one of the first and second clock signals has a preset phase based on a phase of an original clock signal, and wherein the first NPU is configured to operate based on a first phase of the first clock signal, and the second NPU is configured to operate based on a second phase of the second clock signal so that two NPUs including the first NPU and the second NPU operate distributedly in different two phases including the first phase and second phase to reduce a peak power, wherein a phase difference between the first and second clock signals is determined in consideration of a peak power of the SoC. ### Claim 2 (depends on 1) The SoC of claim 1, wherein the at least one of the first and second clock signals is generated by shifting, drifting, or delaying the phase of the original clock signal. ### Claim 3 (depends on 1) The SoC of claim 1, wherein the second phase of the second clock signal is different from the first phase of the first clock signal. ### Claim 4 (depends on 1) The SoC of claim 1, wherein the one or more clock signals include the first clock signal and the second clock signal, and wherein the first phase of the first clock signal is different from the second phase of the second clock signal, and the first phase of the first clock signal is same as a phase of the original clock signal. ### Claim 5 (depends on 1) The SoC of claim 1, wherein the SoC further includes a third circuit for a third NPU, and a third clock signal among the one or more clock signals, is supplied to the third NPU. ### Claim 6 (depends on 1) The SoC of claim 1, wherein a number of the one or more clock signals is preset based on a number of NPUs. ### Claim 7 A system comprising: a substrate; a first semi-conductor chip, mounted on the substrate, provided for a first NPU configured to perform operations of an artificial neural network (ANN) model; a second semi-conductor chip, mounted on the substrate, provided for a second NPU configured to perform operations of an ANN model; and a clock signal supply circuit, mounted on the substrate, configured to output one or more clock signals, wherein each of the first NPU and the second NPU includes a plurality of processing elements (PEs), and the plurality of PEs include an adder, a multiplier, and an accumulator, wherein a first clock signal among the one or more clock signals, is supplied to the first NPU, and a second clock signal among the one or more clock signals, is supplied to the second NPU, wherein at least one of the first and second clock signals has a preset phase based on a phase of an original clock signal, and wherein the first NPU is configured to operate based on a first phase of the first clock signal, and the second NPU is configured to operate based on a second phase of the second clock signal so that two NPUs including the first NPU and the second NPU operate distributedly in different two phases including the first phase and second phase to reduce a peak power, wherein a phase difference between the first and second clock signals is determined in consideration of a peak power of the system. ### Claim 8 (depends on 7) The system of claim 7, wherein the at least one of the first and second clock signals is generated by shifting, drifting, or delaying the phase of the original clock signal. ### Claim 9 (depends on 7) The system of claim 7, wherein the second phase of the second clock signal is different from the first phase of the first clock signal. ### Claim 10 (depends on 7) The system of claim 7, wherein the one or more clock signals include the first clock signal and the second clock signal, and wherein the first phase of the first clock signal is different from the second phase of the second clock signal, and the first phase of the first clock signal is same as a phase of the original clock signal. ### Claim 11 (depends on 7) The system of claim 7, wherein the system further includes a third circuit provided for a third NPU, and a third clock signal among the one or more clock signals, is supplied to the third NPU. ### Claim 12 (depends on 7) The system of claim 7, wherein a number of the one or more clock signals is preset based on a number of NPUs. ### Claim 13 (depends on 7) The system of claim 7, further comprising a system bus, formed of an electrically conductive pattern formed on the substrate, such that the first semi-conductor chip provided for the first NPU, the second semi-conductor chip provided for the second NPU, and the clock signal supply circuit communicate with each other. ### Claim 14 A method of operating a plurality of neural processing units (NPU), comprising: generating a plurality of clock signals including a first clock signal and a second clock signal; and operating a first NPU based on a first phase of the first clock signal while operating a second NPU based on a second phase of the second clock signal so that two NPUs including the first NPU and the second NPU operate distributedly in different two phases including the first phase and second phase, wherein each of the first NPU and the second NPU includes a plurality of processing elements (PEs), and each processing element includes an adder, a multiplier, and an accumulator, wherein at least one of the first and second clock signals has a preset phase based on a phase of an original clock signal to reduce a peak power, wherein a phase difference between the first and second clock signals is determined in consideration of a peak power of the system. ### Claim 15 (depends on 14) The method of claim 14, wherein at least one of the first and second clock signals is generated by shifting, drifting, or delaying a phase of an original clock signal. ### Claim 16 (depends on 14) The method of claim 14, wherein the second phase of the second clock signal is different from the first phase of the first clock signal.