# US 12,117,864 B2 · Interface device and signal transceiving method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,117,864 B2 - Document ID: US12117864B2 - Status: Granted - Kind: B2 - Application number: 17/951,113 - Filed: 2022-09-23 - Published: 2024-01-11 - Granted: 2024-10-15 - Earliest claimed: 2022-07-07 - Assignees: Global Unichip Corporation; Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Global Unichip Corporation; Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Bi-Yang Li; Igor Elkanovich; Hung-Yi Chang; Shih-Cheng Kao - Web page: https://patentgrep.com/patent/US12117864B2 ## CPC - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - H03K 3/0372: {of the primary-secondary type} - H03K 5/22: Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral (indicating phase difference of two cyclic pulse trains G01R25/00) - H04J 3/0685: {Clock or time synchronisation in a node; Intranode synchronisation} - H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F 13/4217: {with synchronous protocol} - G06F 13/423: {with synchronous protocol} - H03K 2005/00019: {Variable delay} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract An interface device and a signal transceiving method thereof are provided. The interface device includes a master circuit and a slave circuit. The slave circuit includes a second receiver, a clock generator, a sampler, and a comparator. The first receiver and second receiver respectively receive input data and a clock signal from the master circuit. The clock generator delays the clock signal according to a delay value to generate a delayed clock signal, and generates a plurality of sampling signals according to the delayed clock signal. The sampler samples the input data according to the sampling signals to generate a plurality of sampling results. The comparator compares the sampling results to generate a comparison result. The clock generator adjusts the delay value according to the comparison result. ## Claims ### Claim 1 An interface device of a semiconductor device, the interface device comprising: a master device, wherein a master circuit is implemented in the master device; and a plurality of slave devices, wherein the slave devices are stacked on the master device to form a three-dimensional structure, wherein a slave circuit is implemented in each of the slave devices, and each of the slave circuits are coupled to the master circuit, wherein each slave circuit comprises: a first receiver, receiving an input data from the master circuit; a second receiver, receiving a first clock signal from the master circuit; a first clock generator, coupled to the second receiver, delaying the first clock signal according to a first delay value to generate a first delayed clock signal, and generating a plurality of first sampling signals according to the first delayed clock signal; a first sampler, sampling the input data according to the first sampling signals to generate a plurality of first sampling results; and a first comparator, coupled to the first sampler, and generating a first comparison result by comparing the first sampling results, wherein the first clock generator adjusts the first delay value according to the first comparison result, wherein when the first sampling results are not all the same, the first comparator causes the first clock generator to increase the first delay value according to the first comparison result, and when the first sampling results are all the same, the first comparator causes the first clock generator to decrease the first delay value according to the first comparison result. ### Claim 2 (depends on 1) The interface device according to claim 1, wherein the first sampling signals respectively have a plurality of different phases. ### Claim 3 (depends on 1) The interface device according to claim 1, wherein the first sampler comprises a plurality of flip-flops, data terminals of the flip-flops receive the input data, clock terminals of the flip-flops respectively receive the first sampling signals, and output terminals of the flip-flops respectively generate the first sampling results. ### Claim 4 (depends on 1) The interface device according to claim 1, wherein the first comparator performs an exclusive OR operation on the first sampling results to generate the first comparison result. ### Claim 5 (depends on 1) The interface device according to claim 1, wherein the first clock generator comprises: a first programmable delay circuit, delaying the first clock signal according to the first delay value to generate the first delayed clock signal; and a first clock tree circuit, coupled to the first programmable delay circuit and generating the first sampling signals according to the first delayed clock signal. ### Claim 6 (depends on 5) The interface device according to claim 5, wherein the first clock generator further comprises: a second clock tree circuit, generating a second clock signal according to the first delayed clock signal, wherein each slave circuit synchronously transmits a transmission data to the master circuit according to the second clock signal. ### Claim 7 (depends on 5) The interface device according to claim 5, wherein the first clock generator further comprises: a second programmable delay circuit, delaying the first clock signal according to a second delay value to generate a second delayed clock signal; and a second clock tree circuit, generating a second clock signal according to the second delayed clock signal, wherein each slave circuit synchronously transmits a transmission data to the master circuit according to the second clock signal. ### Claim 8 (depends on 7) The interface device according to claim 7, wherein the master circuit further comprising: a third clock tree circuit, generating a plurality of second sampling signals according to the second clock signal; a second sampler, sampling the transmission data according to the second sampling signals to generate a plurality of second sampling results; and a second comparator, coupled to the second sampler and generating a second comparison result by comparing the second sampling results, wherein the second programmable delay circuit adjusts the second delay value according to the second comparison result. ### Claim 9 (depends on 8) The interface device according to claim 8, wherein when the second sampling results are not all the same, the second comparator causes the second programmable delay circuit to decrease the second delay value according to the second comparison result, and when the second sampling results are all the same, the second comparator causes the second programmable delay circuit to increase the second delay value according to the second comparison result. ### Claim 10 (depends on 8) The interface device according to claim 8, wherein the second sampler comprises a plurality of flip-flops, data terminals of the flip-flops receive the transmission data, clock terminals of the flip-flops respectively receive the second sampling signals, and output terminals of the flip-flops respectively generate the second sampling results. ### Claim 11 (depends on 8) The interface device according to claim 8, wherein the second comparator performs an exclusive OR operation on the second sampling results to generate the second comparison result. ### Claim 12 (depends on 1) The interface device according to claim 1, wherein in a calibration mode, the master circuit causes at least one bit in the input data to have a plurality of transition edges. ### Claim 13 A signal transceiving method adapted for an interface device of a semiconductor device, wherein the interface device comprises a master device and a plurality of slave devices, and the slave devices are stacked on the master device to form a three-dimensional structure, wherein a master circuit is implemented in the master device, a slave circuit is implemented in each of the slave devices, and each slave circuit is coupled to the master circuit, the signal transceiving method comprising: causing the slave circuit of each of the slave devices to receive an input data and a first clock signal from the master circuit of the master device; delaying the first clock signal according to a first delay value to generate a first delayed clock signal, and generating a plurality of first sampling signals according to the first delayed clock signal; sampling the input data according to the first sampling signals to generate a plurality of first sampling results; generating a first comparison result by comparing the first sampling results; and adjusting the first delay value according to the first comparison results, wherein adjusting the first delay value according to the first comparison result comprises: increasing the first delay value according to the first comparison result when the first sampling results are not all the same; and decreasing the first delay value according to the first comparison result when the first sampling results are all the same. ### Claim 14 (depends on 13) The signal transceiving method according to claim 13, wherein the first sampling signals respectively have a plurality of different phases. ### Claim 15 (depends on 13) The signal transceiving method according to claim 13, further comprising: delaying the first clock signal according to a second delay value to generate a second delayed clock signal; generating a second clock signal according to the second delayed clock signal; and transmitting a transmission data to the master circuit according to the second clock signal. ### Claim 16 (depends on 15) The signal transceiving method according to claim 15, further comprising: generating a plurality of second sampling signals according to the second clock signal; sampling the transmission data according to the second sampling signals to generate a plurality of second sampling results; generating a second comparison result by comparing the second sampling results; and adjusting the second delay value according to the second comparison result. ### Claim 17 (depends on 16) The signal transceiving method according to claim 16, wherein adjusting the second delay value according to the second comparison result comprises: decreasing the second delay value according to the second comparison result when the second sampling results are not all the same; and increasing the second delay value according to the second comparison result when the second sampling results are all the same.